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path: root/drivers/gpu/drm/i915/display/intel_dsb.c
AgeCommit message (Expand)AuthorFilesLines
2024-08-29drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is doneVille Syrjälä1-1/+3
2024-08-29drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANKVille Syrjälä1-5/+38
2024-08-29drm/i915/dsb: Introduce intel_dsb_chain()Ville Syrjälä1-0/+42
2024-08-29drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in,out}()Ville Syrjälä1-0/+73
2024-08-29drm/i915/dsb: Precompute DSB_CHICKENVille Syrjälä1-3/+6
2024-08-29drm/i915/dsb: Account for VRR properly in DSB scanline stuffVille Syrjälä1-5/+60
2024-08-29drm/i915/dsb: Fix dewake scanlineVille Syrjälä1-8/+2
2024-08-29drm/i915/dsb: Shuffle code aroundVille Syrjälä1-28/+28
2024-08-29drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlierVille Syrjälä1-9/+12
2024-08-29drm/i915/dsb: Hook up DSB error interruptsVille Syrjälä1-0/+56
2024-06-20drm/i915/dsb: Add i915.enable_dsb module parameterVille Syrjälä1-0/+3
2024-06-20drm/i915/dsb: Convert the DSB code to use intel_display rather than i915Ville Syrjälä1-26/+26
2024-06-20drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä1-4/+7
2024-06-05drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä1-2/+4
2024-06-05drm/i915/dsb: Move DSB ID definition to the headerVille Syrjälä1-8/+0
2024-06-05drm/i915/dsb: Polish the DSB ID enumVille Syrjälä1-11/+11
2024-05-31drm/i915: drop unnecessary i915_reg.h includesJani Nikula1-1/+0
2024-05-31drm/i915: Reuse intel_mode_vblank_start()Ville Syrjälä1-7/+3
2024-03-07drm/i915/dsb: Always set DSB_SKIP_WAITS_ENVille Syrjälä1-2/+3
2024-03-07drm/i915/dsb: Fix DSB vblank waits when using VRRVille Syrjälä1-0/+14
2024-02-23drm/i915/lnl: Program PKGC_LATENCY registerSuraj Kandpal1-1/+1
2024-01-05drm/i915: Disable DSB in Xe KMDJosé Roberto de Souza1-0/+4
2023-11-29drm/i915: correct the input parameter on _intel_dsb_commit()heminhong1-1/+1
2023-11-16drm/i915/dsb: DSB code refactoringAnimesh Manna1-62/+36
2023-10-13drm/i915/dsb: Correct DSB command buffer cache coherency settingsVille Syrjälä1-4/+11
2023-10-13drm/i915/dsb: Allocate command buffer from local memoryVille Syrjälä1-1/+6
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä1-12/+79
2023-09-27drm/i915/dsb: Add support for non-posted DSB registers writesVille Syrjälä1-0/+20
2023-09-27drm/i915/dsb: Introduce intel_dsb_reg_write_masked()Ville Syrjälä1-0/+18
2023-09-27drm/i915/dsb: Introduce intel_dsb_noop()Ville Syrjälä1-0/+9
2023-09-27drm/i915/dsb: Define the contents of some intstructions bit betterVille Syrjälä1-4/+8
2023-09-27drm/i915/dsb: Use non-locked register accessVille Syrjälä1-9/+9
2023-09-07drm/i915/dsb: Don't use indexed writes when byte enables are not all setVille Syrjälä1-3/+9
2023-09-07drm/i915/dsb: Avoid corrupting the first register writeVille Syrjälä1-0/+8
2023-09-07drm/i915/dsb: Dump the DSB command buffer when DSB failsVille Syrjälä1-3/+30
2023-03-30drm/i915/dsb: split out DSB regs to a separate fileJani Nikula1-0/+1
2023-02-21drm/i915/dsb: Nuke the DSB debugVille Syrjälä1-5/+0
2023-02-20drm/i915/dsb: Allow vblank synchronized DSB executionVille Syrjälä1-1/+3
2023-02-03drm/i915/dsb: Introduce intel_dsb_finish()Ville Syrjälä1-4/+7
2023-02-03drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()Ville Syrjälä1-2/+9
2023-02-03drm/i915/dsb: Pimp debug/error printsVille Syrjälä1-4/+8
2023-01-13drm/i915/dsb: Add mode DSB opcodesVille Syrjälä1-0/+8
2023-01-13drm/i915/dsb: Allow the caller to pass in the DSB buffer sizeVille Syrjälä1-15/+25
2023-01-13drm/i915/dsb: Introduce intel_dsb_align_tail()Ville Syrjälä1-6/+18
2023-01-13drm/i915/dsb: Handle the indexed vs. not inside the DSB codeVille Syrjälä1-56/+34
2023-01-13drm/i915/dsb: Improve the indexed reg write checksVille Syrjälä1-3/+18
2023-01-13drm/i915/dsb: Extract intel_dsb_emit()Ville Syrjälä1-10/+20
2023-01-13drm/i915/dsb: Extract assert_dsb_has_room()Ville Syrjälä1-10/+12
2023-01-13drm/i915/dsb: Fix DSB command buffer size checksVille Syrjälä1-2/+2
2023-01-13drm/i915/dsb: Align DSB register writes to 8 bytesVille Syrjälä1-0/+3
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-01 19:35:07 +0300