diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-12-16 03:38:00 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-01-13 17:48:03 +0300 |
| commit | 3229319e446cafe51e8d3060bdf39203b95a5c98 (patch) | |
| tree | 5cec2b6eb5d29e540d3d61ea11e47748fa4789f1 /drivers/gpu/drm/i915/display/intel_dsb.c | |
| parent | f9e2ada6fed6f0067b1d7380f960bc02dcc8acd2 (diff) | |
| download | linux-3229319e446cafe51e8d3060bdf39203b95a5c98.tar.xz | |
drm/i915/dsb: Align DSB register writes to 8 bytes
Every DSB instruction has to be 8byte aligned. Make sure
that is the case for the non-indexed register writes as well.
The way this could end up unaligned is we emitted an odd
number of indexed register writes beforehand.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221216003810.13338-4-ville.syrjala@linux.intel.com
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dsb.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dsb.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 90a22af30aab..6abfd0fc541a 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -172,6 +172,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, return; } + /* Every instruction should be 8 byte aligned. */ + dsb->free_pos = ALIGN(dsb->free_pos, 2); + dsb->ins_start_offset = dsb->free_pos; buf[dsb->free_pos++] = val; buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | |