diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom')
34 files changed, 970 insertions, 272 deletions
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index f06c6d425e91..0c1d116f6e84 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-lagan-yuga.dtb \ qcom-apq8064-asus-nexus7-flo.dtb \ + qcom-apq8064-lg-nexus4-mako.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index 5dbca83f2230..e6392f7d14c7 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -31,6 +31,15 @@ vsp-supply = <®_lcd_pos>; vsn-supply = <®_lcd_neg>; vddio-supply = <&vddio_disp_vreg>; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; @@ -53,9 +62,12 @@ }; }; + /* TI TPS22902 */ vddio_disp_vreg: regulator-vddio-disp { compatible = "regulator-fixed"; regulator-name = "vddio_disp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; vin-supply = <&pm8226_l8>; startup-delay-us = <300>; @@ -97,6 +109,7 @@ }; &blsp1_i2c2 { + clock-frequency = <100000>; status = "okay"; magnetometer@c { @@ -126,6 +139,7 @@ }; &blsp1_i2c3 { + clock-frequency = <400000>; status = "okay"; regulator@3e { @@ -136,8 +150,8 @@ reg_lcd_pos: outp { regulator-name = "outp"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; regulator-active-discharge = <1>; regulator-boot-on; enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; @@ -145,8 +159,8 @@ reg_lcd_neg: outn { regulator-name = "outn"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; regulator-active-discharge = <1>; regulator-boot-on; enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom/msm8926.dtsi b/arch/arm/boot/dts/qcom/msm8926.dtsi new file mode 100644 index 000000000000..629654c525b4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8926.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss <luca@lucaweiss.eu> + */ + +#include "qcom-msm8226.dtsi" + +&modem { + compatible = "qcom,msm8926-mss-pil"; + /delete-property/ qcom,ext-bhs-reg; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts index da3be658e822..4546fa8beba4 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-samsung-matisse-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts index 7d519156d91d..a8543ca7b556 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts @@ -12,6 +12,8 @@ #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index b3ff8010b149..717bfd74edb7 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -138,7 +138,6 @@ &hdmi { core-vdda-supply = <&pm8921_hdmi_switch>; - hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts new file mode 100644 index 000000000000..c187c6875bc6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +#include "qcom-apq8064-v2.0.dtsi" +#include "pm8821.dtsi" +#include "pm8921.dtsi" + +/ { + model = "LG Nexus 4 (mako)"; + compatible = "lg,nexus4-mako", "qcom,apq8064"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + serial2 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + battery_cell: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <900000>; + operating-range-celsius = <0 45>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000{ + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + }; + }; +}; + +&gsbi1 { + qcom,mode = <GSBI_PROT_I2C>; + + status = "okay"; +}; + +&gsbi1_i2c { + clock-frequency = <200000>; + + status = "okay"; +}; + +&gsbi4 { + qcom,mode = <GSBI_PROT_I2C_UART>; + + status = "okay"; +}; + +&gsbi4_serial { + status = "okay"; +}; + +&pm8821 { + interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921 { + interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921_keypad { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 1, KEY_VOLUMEUP) + >; + + keypad,num-rows = <1>; + keypad,num-columns = <5>; + + status = "okay"; +}; + +&riva { + pinctrl-names = "default"; + pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; + + vddcx-supply = <&pm8921_s3>; + vddmx-supply = <&pm8921_l24>; + vddpx-supply = <&pm8921_s4>; + + status = "okay"; + + iris { + vddxo-supply = <&pm8921_l4>; + vddrfa-supply = <&pm8921_s2>; + vddpa-supply = <&pm8921_l10>; + vdddig-supply = <&pm8921_lvs2>; + }; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + pm8921_l1: l1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi1_pll_vdda */ + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_3p3 */ + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3500000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_1p8 */ + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* msm_sdcc.1-sdc_vdd */ + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + /* earjack_debug */ + pm8921_l6: l6 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi_vci */ + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vddpa */ + pm8921_l10: l10 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi1_avdd */ + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* touch_vdd */ + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + /* slimport_dvdd */ + pm8921_l18: l18 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + bias-pull-down; + }; + + /* touch_io */ + pm8921_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * mipi_dsi.1-dsi_vddio + * pil_qdsp6v4.1-pll_vdd + * pil_qdsp6v4.2-pll_vdd + * msm_ehci_host.0-HSUSB_1p8 + * msm_ehci_host.1-HSUSB_1p8 + */ + pm8921_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * tabla2x-slim-CDC_VDDA_A_1P2V + * tabla2x-slim-VDDD_CDC_D + */ + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + bias-pull-down; + }; + + pm8921_l26: l26 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + bias-pull-down; + }; + + pm8921_l27: l27 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + pm8921_l28: l28 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vddio */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vdddig */ + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + /* mipi_dsi.1-dsi_iovcc */ + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + /* + * pil_riva-pll_vdd + * lvds.0-lvds_vdda + * mipi_dsi.1-dsi1_vddio + * hdmi_msm.0-hdmi_vdda + */ + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* msm otg HSUSB_VDDCX */ + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + /* + * msm_sdcc.1-sdc-vdd_io + * tabla2x-slim-CDC_VDDA_RX + * tabla2x-slim-CDC_VDDA_TX + * tabla2x-slim-CDC_VDD_CP + * tabla2x-slim-VDDIO_CDC + */ + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + + /* + * supply vdd_l26, vdd_l27, vdd_l28 + */ + pm8921_s7: s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s8: s8 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ac7494ed633e..17e506ca2438 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -36,58 +36,58 @@ #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <400>; @@ -213,12 +213,6 @@ }; }; - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; - #hwlock-cells = <1>; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_region>; @@ -284,6 +278,40 @@ }; }; + replicator { + compatible = "arm,coresight-static-replicator"; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&funnel_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -305,9 +333,10 @@ pinctrl-0 = <&ps_hold_default_state>; }; - sfpb_wrapper_mutex: syscon@1200000 { - compatible = "syscon"; - reg = <0x01200000 0x8000>; + sfpb_mutex: hwmutex@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + #hwlock-cells = <1>; }; intc: interrupt-controller@2000000 { @@ -326,6 +355,8 @@ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; @@ -405,8 +436,8 @@ }; }; - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; + sps_sic_non_secure: interrupt-controller@12100000 { + compatible = "qcom,apq8064-sps-sic", "syscon"; reg = <0x12100000 0x10000>; }; @@ -675,7 +706,7 @@ tsens_calib: calib@404 { reg = <0x404 0x10>; }; - tsens_backup: backup_calib@414 { + tsens_backup: backup-calib@414 { reg = <0x414 0x10>; }; }; @@ -737,7 +768,8 @@ <&dsi0_phy 0>, <&dsi1_phy 1>, <&dsi1_phy 0>, - <&hdmi_phy>; + <&hdmi_phy>, + <&mdp>; clock-names = "pxo", "pll3", "pll8_vote", @@ -745,7 +777,8 @@ "dsi1pllbyte", "dsi2pll", "dsi2pllbyte", - "hdmipll"; + "hdmipll", + "lvdspll"; }; l2cc: clock-controller@2011000 { @@ -1089,7 +1122,7 @@ }; mmss_sfpb: syscon@5700000 { - compatible = "syscon"; + compatible = "qcom,apq8064-mmss-sfpb", "syscon"; reg = <0x5700000 0x70>; }; @@ -1404,13 +1437,19 @@ <&mmcc MDP_AXI_CLK>, <&mmcc MDP_LUT_CLK>, <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; + <&mmcc MDP_TV_CLK>, + <&mmcc LVDS_CLK>, + <&rpmcc RPM_PXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_clk", "lut_clk", "hdmi_clk", - "tv_clk"; + "tv_clk", + "lcdc_clk", + "pxo"; + + #clock-cells = <0>; iommus = <&mdp_port0 0 &mdp_port0 2 @@ -1532,39 +1571,6 @@ }; }; - replicator { - compatible = "arm,coresight-static-replicator"; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&funnel_out>; - }; - }; - }; - }; - funnel@1a04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x1a04000 0x1000>; @@ -1625,7 +1631,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU0>; + cpu = <&cpu0>; out-ports { port { @@ -1643,7 +1649,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU1>; + cpu = <&cpu1>; out-ports { port { @@ -1661,7 +1667,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU2>; + cpu = <&cpu2>; out-ports { port { @@ -1679,7 +1685,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU3>; + cpu = <&cpu3>; out-ports { port { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 6fce0112361f..34b0cf35fdac 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -149,7 +149,7 @@ }; &pm8941_gpios { - msm_keys_default: pm8941-gpio-keys-state { + msm_keys_default: pm8941-gpio-keys-state { pins = "gpio5", "gpio23"; function = "normal"; input-enable; @@ -157,7 +157,7 @@ bias-pull-up; qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; power-source = <PM8941_GPIO_S3>; /* 1.8V */ - }; + }; }; &pm8941_lpg { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 014e6c5ee889..cee0694ef127 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -17,7 +17,7 @@ #size-cells = <1>; ranges; - smem_mem: smem_region@fa00000 { + smem_mem: smem-region@fa00000 { reg = <0xfa00000 0x200000>; no-map; }; @@ -32,10 +32,10 @@ compatible = "qcom,krait"; reg = <0>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; cpu@1 { @@ -43,10 +43,10 @@ compatible = "qcom,krait"; reg = <1>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; cpu@2 { @@ -54,10 +54,10 @@ compatible = "qcom,krait"; reg = <2>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; cpu@3 { @@ -65,13 +65,13 @@ compatible = "qcom,krait"; reg = <3>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -79,7 +79,7 @@ }; idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <150>; @@ -311,7 +311,7 @@ bits = <0 6>; }; - tsens_s10_p1: s10_p1@d8 { + tsens_s10_p1: s10-p1@d8 { reg = <0xd8 0x2>; bits = <6 6>; }; @@ -371,137 +371,137 @@ bits = <4 6>; }; - tsens_s10_p2: s10_p2@e2 { + tsens_s10_p2: s10-p2@e2 { reg = <0xe2 0x2>; bits = <2 6>; }; - tsens_s5_p2_backup: s5-p2_backup@e3 { + tsens_s5_p2_backup: s5-p2-backup@e3 { reg = <0xe3 0x2>; bits = <0 6>; }; - tsens_mode_backup: mode_backup@e3 { + tsens_mode_backup: mode-backup@e3 { reg = <0xe3 0x1>; bits = <6 2>; }; - tsens_s6_p2_backup: s6-p2_backup@e4 { + tsens_s6_p2_backup: s6-p2-backup@e4 { reg = <0xe4 0x1>; bits = <0 6>; }; - tsens_s7_p2_backup: s7-p2_backup@e4 { + tsens_s7_p2_backup: s7-p2-backup@e4 { reg = <0xe4 0x2>; bits = <6 6>; }; - tsens_s8_p2_backup: s8-p2_backup@e5 { + tsens_s8_p2_backup: s8-p2-backup@e5 { reg = <0xe5 0x2>; bits = <4 6>; }; - tsens_s9_p2_backup: s9-p2_backup@e6 { + tsens_s9_p2_backup: s9-p2-backup@e6 { reg = <0xe6 0x2>; bits = <2 6>; }; - tsens_s10_p2_backup: s10_p2_backup@e7 { + tsens_s10_p2_backup: s10-p2-backup@e7 { reg = <0xe7 0x1>; bits = <0 6>; }; - tsens_base1_backup: base1_backup@440 { + tsens_base1_backup: base1-backup@440 { reg = <0x440 0x1>; bits = <0 8>; }; - tsens_s0_p1_backup: s0-p1_backup@441 { + tsens_s0_p1_backup: s0-p1-backup@441 { reg = <0x441 0x1>; bits = <0 6>; }; - tsens_s1_p1_backup: s1-p1_backup@442 { + tsens_s1_p1_backup: s1-p1-backup@442 { reg = <0x441 0x2>; bits = <6 6>; }; - tsens_s2_p1_backup: s2-p1_backup@442 { + tsens_s2_p1_backup: s2-p1-backup@442 { reg = <0x442 0x2>; bits = <4 6>; }; - tsens_s3_p1_backup: s3-p1_backup@443 { + tsens_s3_p1_backup: s3-p1-backup@443 { reg = <0x443 0x1>; bits = <2 6>; }; - tsens_s4_p1_backup: s4-p1_backup@444 { + tsens_s4_p1_backup: s4-p1-backup@444 { reg = <0x444 0x1>; bits = <0 6>; }; - tsens_s5_p1_backup: s5-p1_backup@444 { + tsens_s5_p1_backup: s5-p1-backup@444 { reg = <0x444 0x2>; bits = <6 6>; }; - tsens_s6_p1_backup: s6-p1_backup@445 { + tsens_s6_p1_backup: s6-p1-backup@445 { reg = <0x445 0x2>; bits = <4 6>; }; - tsens_s7_p1_backup: s7-p1_backup@446 { + tsens_s7_p1_backup: s7-p1-backup@446 { reg = <0x446 0x1>; bits = <2 6>; }; - tsens_use_backup: use_backup@447 { + tsens_use_backup: use-backup@447 { reg = <0x447 0x1>; bits = <5 3>; }; - tsens_s8_p1_backup: s8-p1_backup@448 { + tsens_s8_p1_backup: s8-p1-backup@448 { reg = <0x448 0x1>; bits = <0 6>; }; - tsens_s9_p1_backup: s9-p1_backup@448 { + tsens_s9_p1_backup: s9-p1-backup@448 { reg = <0x448 0x2>; bits = <6 6>; }; - tsens_s10_p1_backup: s10_p1_backup@449 { + tsens_s10_p1_backup: s10-p1-backup@449 { reg = <0x449 0x2>; bits = <4 6>; }; - tsens_base2_backup: base2_backup@44a { + tsens_base2_backup: base2-backup@44a { reg = <0x44a 0x2>; bits = <2 8>; }; - tsens_s0_p2_backup: s0-p2_backup@44b { + tsens_s0_p2_backup: s0-p2-backup@44b { reg = <0x44b 0x3>; bits = <2 6>; }; - tsens_s1_p2_backup: s1-p2_backup@44c { + tsens_s1_p2_backup: s1-p2-backup@44c { reg = <0x44c 0x1>; bits = <0 6>; }; - tsens_s2_p2_backup: s2-p2_backup@44c { + tsens_s2_p2_backup: s2-p2-backup@44c { reg = <0x44c 0x2>; bits = <6 6>; }; - tsens_s3_p2_backup: s3-p2_backup@44d { + tsens_s3_p2_backup: s3-p2-backup@44d { reg = <0x44d 0x2>; bits = <4 6>; }; - tsens_s4_p2_backup: s4-p2_backup@44e { + tsens_s4_p2_backup: s4-p2-backup@44e { reg = <0x44e 0x1>; bits = <2 6>; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index 0d23c03fae33..be76bc39ac27 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -166,16 +166,19 @@ label = "ART"; reg = <0x00170000 0x00010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; }; @@ -248,7 +251,7 @@ status = "okay"; nvmem-cell-names = "pre-calibration"; nvmem-cells = <&precal_art_5000>; - qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; + qcom,calibration-variant = "ALFA-Network-AP120C-AC"; }; &usb3_hs_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts index ac3b30072a22..15baaf0d1529 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -25,7 +25,7 @@ }; }; - serial_pins: serial-state{ + serial_pins: serial-state { pins = "gpio60", "gpio61"; function = "blsp_uart0"; bias-disable; @@ -179,13 +179,13 @@ &wifi0 { status = "okay"; - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; + qcom,calibration-variant = "8devices-Jalapeno"; }; &wifi1 { status = "okay"; - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; + qcom,calibration-variant = "8devices-Jalapeno"; }; &usb3_ss_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi index cc88cf5f0d9b..5a95a2d03c42 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -43,7 +43,7 @@ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69"; function = "qpic"; - }; + }; }; serial@78af000 { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 56415ab34083..f77542fb3d4f 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -47,13 +47,12 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -61,13 +60,12 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -75,13 +73,12 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -89,17 +86,16 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -126,7 +122,7 @@ opp-716000000 { opp-hz = /bits/ 64 <716000000>; clock-latency-ns = <256000>; - }; + }; }; memory { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 759a59c2bdbc..96e973501535 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -27,7 +27,7 @@ enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; }; @@ -37,12 +37,12 @@ enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -383,7 +383,7 @@ tsens_calib: calib@400 { reg = <0x400 0xb>; }; - tsens_calib_backup: calib_backup@410 { + tsens_calib_backup: calib-backup@410 { reg = <0x410 0xb>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 573feb3218c3..7de8d6c55016 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -30,7 +30,7 @@ compatible = "arm,cortex-a5"; reg = <0>; device_type = "cpu"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; }; }; @@ -61,7 +61,7 @@ ranges; compatible = "simple-bus"; - L2: cache-controller@2040000 { + l2: cache-controller@2040000 { compatible = "arm,pl310-cache"; reg = <0x02040000 0x1000>; arm,data-latency = <2 2 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi index ca76bf8af75e..d4a32af0ef8f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi @@ -8,7 +8,11 @@ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh> */ -#include "qcom-msm8226.dtsi" +/* + * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on + * the SoC on the given device. + */ + #include "pm8226.dtsi" #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts index 2c664b5934ec..f448c9088416 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts index 731c5c375678..94bf3b1ad1bd 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts index a28a83cb5340..d8cdb75dfbb8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has no magnetometer */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi index a15a44fc0181..f1544a7e8369 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -3,11 +3,17 @@ * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com> */ +/* + * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on + * the SoC on the given device. + */ + #include <dt-bindings/input/input.h> -#include "qcom-msm8226.dtsi" #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { @@ -145,12 +151,12 @@ no-map; }; - mpss@8400000 { + mpss_region: mpss@8400000 { reg = <0x08400000 0x1f00000>; no-map; }; - mba@a300000 { + mba_region: mba@a300000 { reg = <0x0a300000 0x100000>; no-map; }; @@ -223,6 +229,13 @@ status = "okay"; }; +&modem { + mx-supply = <&pm8226_l3>; + pll-supply = <&pm8226_l8>; + + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm8226-regulators"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 3a685ff7e8cc..51a7a3fb36d8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -39,12 +40,12 @@ #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc0>; @@ -52,12 +53,12 @@ #cooling-cells = <2>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc1>; @@ -65,12 +66,12 @@ #cooling-cells = <2>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc2>; @@ -78,12 +79,12 @@ #cooling-cells = <2>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc3>; @@ -91,7 +92,7 @@ #cooling-cells = <2>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -213,6 +214,18 @@ no-map; }; + mpss_region: mpss@8000000 { + reg = <0x08000000 0x5100000>; + no-map; + status = "disabled"; + }; + + mba_region: mba@d100000 { + reg = <0x0d100000 0x100000>; + no-map; + status = "disabled"; + }; + adsp_region: adsp@dc00000 { reg = <0x0dc00000 0x1900000>; no-map; @@ -253,6 +266,65 @@ }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -845,12 +917,96 @@ #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + + modem: remoteproc@fc880000 { + compatible = "qcom,msm8226-mss-pil"; + reg = <0xfc880000 0x4040>, + <0xfc820000 0x10000>; + reg-names = "qdsp6", + "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "bus", + "mem", + "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>; + qcom,halt-regs = <&tcsr_regs_1 0x180 0x200 0x280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + memory-region = <&mba_region>, <&mpss_region>; + + status = "disabled"; + + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + tcsr_mutex: hwlock@fd484000 { compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; reg = <0xfd484000 0x1000>; #hwlock-cells = <1>; }; + tcsr_regs_1: syscon@fd485000 { + compatible = "qcom,tcsr-msm8226", "syscon"; + reg = <0xfd485000 0x1000>; + }; + tlmm: pinctrl@fd510000 { compatible = "qcom,msm8226-pinctrl"; reg = <0xfd510000 0x4000>; @@ -983,8 +1139,8 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "mmss_gpll0_vote", "gpll0_vote", @@ -1060,8 +1216,8 @@ assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -1264,10 +1420,10 @@ cooling-maps { map0 { trip = <&cpu_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; @@ -1295,10 +1451,10 @@ cooling-maps { map0 { trip = <&cpu_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index a66c474cd1aa..3f69b98d0041 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -22,7 +22,7 @@ enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; }; cpu@1 { @@ -30,10 +30,10 @@ enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi index 1ba403b83cb1..94b7694eeeff 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi @@ -25,7 +25,7 @@ }; }; -&CPU_SLEEP_0 { +&cpu_sleep_0 { compatible = "qcom,idle-state-spc", "arm,idle-state"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts index 3037344eb240..cb571aa13c11 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts @@ -5,10 +5,12 @@ /dts-v1/; -#include "qcom-msm8226.dtsi" +#include "msm8926.dtsi" #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { @@ -193,6 +195,16 @@ /* TPS61310 Flash/Torch @ 33 */ }; +&modem { + mx-supply = <&pm8226_l3>; + pll-supply = <&pm8226_l8>; + mss-supply = <&pm8226_s5>; + + firmware-name = "qcom/msm8926/memul/mba.b00", "qcom/msm8926/memul/modem.mdt"; + + status = "okay"; +}; + &pm8226_vib { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts index 9b48661d69c5..eea4fd8cd972 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has touchscreen on i2c3 instead */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts index 55077a5f2e34..f23bbb94cc5e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has touchscreen on i2c1 instead */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index 376a33125941..db3273c755c2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "qcom-msm8226.dtsi" +#include "msm8926.dtsi" #include "pm8226.dtsi" /delete-node/ &smem_region; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts index d0e1bc39f8ef..73e19176eb97 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-samsung-matisse-common.dtsi" / { @@ -27,6 +28,10 @@ }; }; +&modem { + mss-supply = <&pm8226_s5>; +}; + &tlmm { tsp_en1_default_state: tsp-en1-default-state { pins = "gpio32"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index ebc43c5c6e5f..4babd0bbe5d6 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -25,7 +25,7 @@ enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; }; @@ -35,12 +35,12 @@ enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -52,6 +52,48 @@ reg = <0x80000000 0>; }; + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 0>; + + trips { + cpu_alert0: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 1>; + + trips { + cpu_alert1: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <GIC_PPI 10 0x304>; @@ -112,9 +154,26 @@ <GIC_PPI 3 0x301>; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; + qfprom: efuse@700000 { + compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_calib: calib@404 { + reg = <0x404 0x10>; + }; + + tsens_backup: backup-calib@414 { + reg = <0x414 0x10>; + }; + }; + msmgpio: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; gpio-controller; @@ -127,7 +186,7 @@ }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; + compatible = "qcom,gcc-msm8960", "syscon"; #clock-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; @@ -135,6 +194,18 @@ <&pxo_board>, <&lcc PLL4>; clock-names = "cxo", "pxo", "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { @@ -279,7 +350,7 @@ compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; - reg = <0x12180000 0x8000>; + reg = <0x12180000 0x2000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -289,13 +360,25 @@ max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x4000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; sdcc1: mmc@12400000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; + reg = <0x12400000 0x2000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -305,6 +388,18 @@ cap-sd-highspeed; cap-mmc-highspeed; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; tcsr: syscon@1a400000 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index fdb6e22986cf..261044fdfee8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -167,7 +167,7 @@ status = "okay"; clock-frequency = <100000>; - avago_apds993@39 { + sensor@39 { compatible = "avago,apds9930"; reg = <0x39>; interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 1bd87170252d..7e119370f337 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interconnect/qcom,msm8974.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -35,51 +36,51 @@ #size-cells = <0>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - CPU0: cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -87,7 +88,7 @@ }; idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <150>; @@ -960,7 +961,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU0>; + cpu = <&cpu0>; out-ports { port { @@ -978,7 +979,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU1>; + cpu = <&cpu1>; out-ports { port { @@ -996,7 +997,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU2>; + cpu = <&cpu2>; out-ports { port { @@ -1014,7 +1015,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU3>; + cpu = <&cpu3>; out-ports { port { @@ -1299,7 +1300,7 @@ bits = <0 6>; }; - tsens_s10_p1: s10_p1@d8 { + tsens_s10_p1: s10-p1@d8 { reg = <0xd8 0x2>; bits = <6 6>; }; @@ -1359,137 +1360,137 @@ bits = <4 6>; }; - tsens_s10_p2: s10_p2@e2 { + tsens_s10_p2: s10-p2@e2 { reg = <0xe2 0x2>; bits = <2 6>; }; - tsens_s5_p2_backup: s5-p2_backup@e3 { + tsens_s5_p2_backup: s5-p2-backup@e3 { reg = <0xe3 0x2>; bits = <0 6>; }; - tsens_mode_backup: mode_backup@e3 { + tsens_mode_backup: mode-backup@e3 { reg = <0xe3 0x1>; bits = <6 2>; }; - tsens_s6_p2_backup: s6-p2_backup@e4 { + tsens_s6_p2_backup: s6-p2-backup@e4 { reg = <0xe4 0x1>; bits = <0 6>; }; - tsens_s7_p2_backup: s7-p2_backup@e4 { + tsens_s7_p2_backup: s7-p2-backup@e4 { reg = <0xe4 0x2>; bits = <6 6>; }; - tsens_s8_p2_backup: s8-p2_backup@e5 { + tsens_s8_p2_backup: s8-p2-backup@e5 { reg = <0xe5 0x2>; bits = <4 6>; }; - tsens_s9_p2_backup: s9-p2_backup@e6 { + tsens_s9_p2_backup: s9-p2-backup@e6 { reg = <0xe6 0x2>; bits = <2 6>; }; - tsens_s10_p2_backup: s10_p2_backup@e7 { + tsens_s10_p2_backup: s10-p2-backup@e7 { reg = <0xe7 0x1>; bits = <0 6>; }; - tsens_base1_backup: base1_backup@440 { + tsens_base1_backup: base1-backup@440 { reg = <0x440 0x1>; bits = <0 8>; }; - tsens_s0_p1_backup: s0-p1_backup@441 { + tsens_s0_p1_backup: s0-p1-backup@441 { reg = <0x441 0x1>; bits = <0 6>; }; - tsens_s1_p1_backup: s1-p1_backup@442 { + tsens_s1_p1_backup: s1-p1-backup@442 { reg = <0x441 0x2>; bits = <6 6>; }; - tsens_s2_p1_backup: s2-p1_backup@442 { + tsens_s2_p1_backup: s2-p1-backup@442 { reg = <0x442 0x2>; bits = <4 6>; }; - tsens_s3_p1_backup: s3-p1_backup@443 { + tsens_s3_p1_backup: s3-p1-backup@443 { reg = <0x443 0x1>; bits = <2 6>; }; - tsens_s4_p1_backup: s4-p1_backup@444 { + tsens_s4_p1_backup: s4-p1-backup@444 { reg = <0x444 0x1>; bits = <0 6>; }; - tsens_s5_p1_backup: s5-p1_backup@444 { + tsens_s5_p1_backup: s5-p1-backup@444 { reg = <0x444 0x2>; bits = <6 6>; }; - tsens_s6_p1_backup: s6-p1_backup@445 { + tsens_s6_p1_backup: s6-p1-backup@445 { reg = <0x445 0x2>; bits = <4 6>; }; - tsens_s7_p1_backup: s7-p1_backup@446 { + tsens_s7_p1_backup: s7-p1-backup@446 { reg = <0x446 0x1>; bits = <2 6>; }; - tsens_use_backup: use_backup@447 { + tsens_use_backup: use-backup@447 { reg = <0x447 0x1>; bits = <5 3>; }; - tsens_s8_p1_backup: s8-p1_backup@448 { + tsens_s8_p1_backup: s8-p1-backup@448 { reg = <0x448 0x1>; bits = <0 6>; }; - tsens_s9_p1_backup: s9-p1_backup@448 { + tsens_s9_p1_backup: s9-p1-backup@448 { reg = <0x448 0x2>; bits = <6 6>; }; - tsens_s10_p1_backup: s10_p1_backup@449 { + tsens_s10_p1_backup: s10-p1-backup@449 { reg = <0x449 0x2>; bits = <4 6>; }; - tsens_base2_backup: base2_backup@44a { + tsens_base2_backup: base2-backup@44a { reg = <0x44a 0x2>; bits = <2 8>; }; - tsens_s0_p2_backup: s0-p2_backup@44b { + tsens_s0_p2_backup: s0-p2-backup@44b { reg = <0x44b 0x3>; bits = <2 6>; }; - tsens_s1_p2_backup: s1-p2_backup@44c { + tsens_s1_p2_backup: s1-p2-backup@44c { reg = <0x44c 0x1>; bits = <0 6>; }; - tsens_s2_p2_backup: s2-p2_backup@44c { + tsens_s2_p2_backup: s2-p2-backup@44c { reg = <0x44c 0x2>; bits = <6 6>; }; - tsens_s3_p2_backup: s3-p2_backup@44d { + tsens_s3_p2_backup: s3-p2-backup@44d { reg = <0x44d 0x2>; bits = <4 6>; }; - tsens_s4_p2_backup: s4-p2_backup@44e { + tsens_s4_p2_backup: s4-p2-backup@44e { reg = <0x44e 0x1>; bits = <2 6>; }; @@ -1871,10 +1872,10 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>; @@ -1961,8 +1962,10 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -2032,8 +2035,10 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..20fdae9825e0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -57,7 +57,7 @@ enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; @@ -427,8 +427,9 @@ interrupt-names = "global", "doorbell"; - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "pcie-mem"; + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; @@ -437,6 +438,7 @@ phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -612,6 +614,8 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..c8e312dcd26b 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -58,7 +58,7 @@ enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX65_CX_AO>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; @@ -335,6 +335,10 @@ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; @@ -345,6 +349,7 @@ max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -525,6 +530,8 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -592,39 +599,39 @@ reg = <0x15000000 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; }; intc: interrupt-controller@17800000 { |