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Diffstat (limited to 'arch/arm/boot/dts/qcom/qcom-msm8974.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom/qcom-msm8974.dtsi113
1 files changed, 59 insertions, 54 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index 1bd87170252d..7e119370f337 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interconnect/qcom,msm8974.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
@@ -35,51 +36,51 @@
#size-cells = <0>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <1>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <2>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <3>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- L2: l2-cache {
+ l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -87,7 +88,7 @@
};
idle-states {
- CPU_SPC: cpu-spc {
+ cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
@@ -960,7 +961,7 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
out-ports {
port {
@@ -978,7 +979,7 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
out-ports {
port {
@@ -996,7 +997,7 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
out-ports {
port {
@@ -1014,7 +1015,7 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
out-ports {
port {
@@ -1299,7 +1300,7 @@
bits = <0 6>;
};
- tsens_s10_p1: s10_p1@d8 {
+ tsens_s10_p1: s10-p1@d8 {
reg = <0xd8 0x2>;
bits = <6 6>;
};
@@ -1359,137 +1360,137 @@
bits = <4 6>;
};
- tsens_s10_p2: s10_p2@e2 {
+ tsens_s10_p2: s10-p2@e2 {
reg = <0xe2 0x2>;
bits = <2 6>;
};
- tsens_s5_p2_backup: s5-p2_backup@e3 {
+ tsens_s5_p2_backup: s5-p2-backup@e3 {
reg = <0xe3 0x2>;
bits = <0 6>;
};
- tsens_mode_backup: mode_backup@e3 {
+ tsens_mode_backup: mode-backup@e3 {
reg = <0xe3 0x1>;
bits = <6 2>;
};
- tsens_s6_p2_backup: s6-p2_backup@e4 {
+ tsens_s6_p2_backup: s6-p2-backup@e4 {
reg = <0xe4 0x1>;
bits = <0 6>;
};
- tsens_s7_p2_backup: s7-p2_backup@e4 {
+ tsens_s7_p2_backup: s7-p2-backup@e4 {
reg = <0xe4 0x2>;
bits = <6 6>;
};
- tsens_s8_p2_backup: s8-p2_backup@e5 {
+ tsens_s8_p2_backup: s8-p2-backup@e5 {
reg = <0xe5 0x2>;
bits = <4 6>;
};
- tsens_s9_p2_backup: s9-p2_backup@e6 {
+ tsens_s9_p2_backup: s9-p2-backup@e6 {
reg = <0xe6 0x2>;
bits = <2 6>;
};
- tsens_s10_p2_backup: s10_p2_backup@e7 {
+ tsens_s10_p2_backup: s10-p2-backup@e7 {
reg = <0xe7 0x1>;
bits = <0 6>;
};
- tsens_base1_backup: base1_backup@440 {
+ tsens_base1_backup: base1-backup@440 {
reg = <0x440 0x1>;
bits = <0 8>;
};
- tsens_s0_p1_backup: s0-p1_backup@441 {
+ tsens_s0_p1_backup: s0-p1-backup@441 {
reg = <0x441 0x1>;
bits = <0 6>;
};
- tsens_s1_p1_backup: s1-p1_backup@442 {
+ tsens_s1_p1_backup: s1-p1-backup@442 {
reg = <0x441 0x2>;
bits = <6 6>;
};
- tsens_s2_p1_backup: s2-p1_backup@442 {
+ tsens_s2_p1_backup: s2-p1-backup@442 {
reg = <0x442 0x2>;
bits = <4 6>;
};
- tsens_s3_p1_backup: s3-p1_backup@443 {
+ tsens_s3_p1_backup: s3-p1-backup@443 {
reg = <0x443 0x1>;
bits = <2 6>;
};
- tsens_s4_p1_backup: s4-p1_backup@444 {
+ tsens_s4_p1_backup: s4-p1-backup@444 {
reg = <0x444 0x1>;
bits = <0 6>;
};
- tsens_s5_p1_backup: s5-p1_backup@444 {
+ tsens_s5_p1_backup: s5-p1-backup@444 {
reg = <0x444 0x2>;
bits = <6 6>;
};
- tsens_s6_p1_backup: s6-p1_backup@445 {
+ tsens_s6_p1_backup: s6-p1-backup@445 {
reg = <0x445 0x2>;
bits = <4 6>;
};
- tsens_s7_p1_backup: s7-p1_backup@446 {
+ tsens_s7_p1_backup: s7-p1-backup@446 {
reg = <0x446 0x1>;
bits = <2 6>;
};
- tsens_use_backup: use_backup@447 {
+ tsens_use_backup: use-backup@447 {
reg = <0x447 0x1>;
bits = <5 3>;
};
- tsens_s8_p1_backup: s8-p1_backup@448 {
+ tsens_s8_p1_backup: s8-p1-backup@448 {
reg = <0x448 0x1>;
bits = <0 6>;
};
- tsens_s9_p1_backup: s9-p1_backup@448 {
+ tsens_s9_p1_backup: s9-p1-backup@448 {
reg = <0x448 0x2>;
bits = <6 6>;
};
- tsens_s10_p1_backup: s10_p1_backup@449 {
+ tsens_s10_p1_backup: s10-p1-backup@449 {
reg = <0x449 0x2>;
bits = <4 6>;
};
- tsens_base2_backup: base2_backup@44a {
+ tsens_base2_backup: base2-backup@44a {
reg = <0x44a 0x2>;
bits = <2 8>;
};
- tsens_s0_p2_backup: s0-p2_backup@44b {
+ tsens_s0_p2_backup: s0-p2-backup@44b {
reg = <0x44b 0x3>;
bits = <2 6>;
};
- tsens_s1_p2_backup: s1-p2_backup@44c {
+ tsens_s1_p2_backup: s1-p2-backup@44c {
reg = <0x44c 0x1>;
bits = <0 6>;
};
- tsens_s2_p2_backup: s2-p2_backup@44c {
+ tsens_s2_p2_backup: s2-p2-backup@44c {
reg = <0x44c 0x2>;
bits = <6 6>;
};
- tsens_s3_p2_backup: s3-p2_backup@44d {
+ tsens_s3_p2_backup: s3-p2-backup@44d {
reg = <0x44d 0x2>;
bits = <4 6>;
};
- tsens_s4_p2_backup: s4-p2_backup@44e {
+ tsens_s4_p2_backup: s4-p2-backup@44e {
reg = <0x44e 0x1>;
bits = <2 6>;
};
@@ -1871,10 +1872,10 @@
<&gcc GPLL0_VOTE>,
<&gcc GPLL1_VOTE>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
- <&mdss_dsi0_phy 1>,
- <&mdss_dsi0_phy 0>,
- <&mdss_dsi1_phy 1>,
- <&mdss_dsi1_phy 0>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
<0>,
<0>,
<0>;
@@ -1961,8 +1962,10 @@
interrupt-parent = <&mdss>;
interrupts = <4>;
- assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+ assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
+ <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
@@ -2032,8 +2035,10 @@
interrupt-parent = <&mdss>;
interrupts = <4>;
- assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+ assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
+ <&mmcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-27 00:44:41 +0300