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2026-01-18dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur PlatformsJingyi Wang1-0/+2
Document the Inter-Processor Communication Controller on the Qualcomm Kaanapali and Glymur Platforms, which will be used to route interrupts across various subsystems found on the SoC. Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for KaanapaliJingyi Wang1-0/+1
Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm Kaanapali, which is compatible with X1E80100, use fallback to indicate this. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16arm64: dts: qcom: lemans: enable static TPDMJie Gan1-0/+105
Enable static TPDM device for lemans. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20251028-add_static_tpdm_support-v4-3-84e21b98e727@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16arm64: dts: qcom: kodiak: Add memory region for audiopdJianping Li1-0/+8
Add reserved memory region for audio PD dynamic loading and remote heap requirement. Also add LPASS and ADSP_HEAP VMIDs. Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251117070819.492-1-jianping.li@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodesNeil Armstrong1-0/+81
The Thinkpad T14s embeds a transparent 4lanes DP->HDMI transceiver connected to the third QMP Combo PHY 4 lanes. Add all the data routing, disable mode switching and specify the QMP Combo PHY should be in DP-Only mode to route the 4 lanes to the underlying DP phy. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20251119-topic-x1e80100-hdmi-v7-3-2bee0e66cc1b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models)Jonathan Marek1-2/+2
Unlike the phone SoCs this was copied from, x1e has a 40-bit physical bus. The upper address space is used to support more than 32GB of memory. This fixes issues when DMA buffers are allocated outside the 36-bit range. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251127212943.24480-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16arm64: dts: qcom: lemans; Add EL2 overlayMukesh Ojha2-0/+45
All the Lemans IOT variants boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Lemans IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260105-kvmrprocv10-v10-14-022e96815380@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-15arm64: dts: qcom: sm8150: add uart13Dmitry Baryshkov1-0/+9
Add UART13, typically used for Bluetooth connection on SM8150. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-9-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-15arm64: dts: qcom: sdm845-db845c: specify power for WiFi CH1Dmitry Baryshkov1-0/+7
Specify power supply for the second chain / antenna output of the onboard WiFi chip. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-8-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-15arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0Dmitry Baryshkov1-1/+0
On SDM845 SPI uses hardware-provided chip select, while specifying cs-gpio makes the driver request GPIO pin, which on DB845c conflicts with the normal host controllers pinctrl entry. Drop the cs-gpios property to restore SPI functionality. Fixes: cb29e7106d4e ("arm64: dts: qcom: db845c: Add support for MCP2517FD") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-7-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-15arm64: dts: qcom: qrb4210-rb2: Fix UART3 wakeup IRQ stormDmitry Baryshkov1-1/+1
Follow commit 9c92d36b0b1e ("arm64: dts: qcom: qrb2210-rb1: Fix UART3 wakeup IRQ storm") and apply the similar fix to the RB2 platform. Having RX / TX pins as pull up and wakup interrupt as high-level triggered generates an interrupt storm when trying to suspend the device. Avoid the storm by using the falling edge trigger (as all other platforms do). Fixes: cab60b166575 ("arm64: dts: qcom: qrb4210-rb2: Enable bluetooth") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-6-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-15arm64: dts: qcom: sm6125-ginkgo: Fix missing msm-id subtypeKrzysztof Kozlowski1-1/+1
qcom,msm-id property must consist of two numbers, where the second number is the subtype, as reported by dtbs_check: sm6125-xiaomi-ginkgo.dtb: / (xiaomi,ginkgo): qcom,msm-id:0: [394] is too short Xiaomi vendor DTS for Trinket IDP and QRD boards uses value of 0x10000, so put it here as well. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251229142806.241088-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-13arm64: dts: qcom: qcs8300: Add GPU coolingGaurav Kohli1-0/+26
Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when reaching 115°C. Signed-off-by: Gaurav Kohli <quic_gkohli@quicinc.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250903-a623-gpu-support-v5-4-5398585e2981@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-13arm64: dts: qcom: sa8775p: Add reg and clocks for QoS configurationOdelu Kukatla1-72/+91
Add register addresses and clocks which need to be enabled for configuring QoS on sa8775p SoC. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251001073344.6599-4-odelu.kukatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: hamoa-iot-evk: Enable TPM (ST33) on SPI11Khalid Faisal Ansari1-0/+10
Enable ST33HTPM TPM over SPI11 on the Hamoa IoT EVK by adding the required SPI and TPM nodes. Signed-off-by: Khalid Faisal Ansari <khalid.ansari@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251112-arm64-dts-qcom-hamoa-iot-evk-enable-st33-tpm-on-spi11-v3-1-39b19eb55cc3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: talos: Add PMU supportYuanjie Yang1-0/+20
Add the PMU node for talos platforms. Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260108092542.1371-3-yuanjie.yang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitionsYuanjie Yang1-154/+154
The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260108092542.1371-2-yuanjie.yang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: ipq9574: Complete USB DWC3 wrapper interruptsKrzysztof Kozlowski1-2/+8
Complete interrupts for DWC3 node to match what is required by Devicetree bindings, as reported by dtbs_check: ipq9574-rdp433.dtb: usb@8af8800 (qcom,ipq9574-dwc3): interrupt-names: ['pwr_event'] is too short The actual interrupt numbers are taken from reference manual of similar chip, but not IPQ9574, due to lack of access to it. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Tested-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106185123.19929-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interruptsKrzysztof Kozlowski1-2/+6
Interrupts for DWC3 node were completely mixed up - SPI interrupt 62 is not listed in reference manual at all. It was also causing dtbs_check warnings: ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names:0: 'pwr_event' was expected ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names: ['hs_phy_irq'] is too short Warning itself was introduced by commit 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding"), but this was trying to bring sanity to the interrupts overall, although did a mistake for IPQ5018. IPQ5018 does not have QUSB2 PHY and its interrupts should rather match ones used in IPQ5332. Correct it by using interrupts matching the bindings and reference manual. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20260106185123.19929-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: monaco: Add CTCU and ETR nodesJie Gan1-0/+153
Add CTCU and ETR nodes in DT to enable expected functionalities. Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251103-enable-ctcu-for-monaco-v4-2-92ff83201584@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK boardZiyue Zhang2-6/+97
HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality and PCIe3 to connect a SATA controller. These interfaces require multiple voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs. Add the required fixed regulators with related pin configuration, and connect them to the PCIe3 and PCIe5 ports to ensure proper power for the SDX65 module and SATA controller. Move reset and wake GPIO properties from RC nodes to port nodes. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260109104504.3147745-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: Add PCIe3 and PCIe5 support for HAMOA-IOT-SOM platformZiyue Zhang1-0/+74
HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller and SDX65. Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states and power supply properties in the device tree, which PCIe3 and PCIe5 require. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260109104504.3147745-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes ↵Ziyue Zhang9-61/+108
and add port Nodes for all PCIe ports Since describing the PCIe PHY directly under the RC node is now deprecated, move the references to the respective PCIe port nodes, creating them where necessary.Also add port nodes for PCIe5 and PCIe6a with proper PHY references. And also move the PCIe PERST and wake GPIOs from the controller nodes to the corresponding PCIe port nodes on Hamoa-based platforms: - x1e001de-devkit - x1e78100-lenovo-thinkpad-t14s - x1e80100-asus-vivobook-s15 - x1e80100-asus-zenbook-a14 - x1e80100-dell-xps13-9345 - x1e80100-lenovo-yoga-slim7x - x1e80100-microsoft-romulus - x1e80100-qcp Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260109104504.3147745-2-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: sdm630: Add LPASS LPI TLMMRichard Acayan1-0/+73
The LPASS LPI TLMM pin controller controls pins for use by the analog and digital codecs, such as the PDM bus, the digital microphone pins, and the compander pins. Add it to support the codecs. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Co-developed-by: Nickolay Goppen <setotau@mainlining.org> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260109-qcom-sdm660-lpass-lpi-dts-v1-1-d3eb84f10a39@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: kodiak: Add missing clock votes for lpass_tlmmLuca Weiss2-0/+10
Without the correct clock votes set, we may be hitting a synchronous external abort error when touching the lpi registers. Internal error: synchronous external abort: 0000000096000010 [#1] SMP <...> Call trace: lpi_gpio_read.isra.0+0x2c/0x58 (P) pinmux_enable_setting+0x218/0x300 pinctrl_commit_state+0xb0/0x280 pinctrl_select_state+0x28/0x48 pinctrl_bind_pins+0x1f4/0x2a0 really_probe+0x64/0x3a8 Add the clocks to fix that. Platforms with this SoC using AudioReach won't be impacted due to qcs6490-audioreach.dtsi already setting clocks & clock-names for q6prmcc. The sc7280-chrome-common.dtsi has also been adjusted to keep the behavior the same as they also do not use Elite with q6afecc. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Tested-by: Bhushan Shah <bhushan.shah@machinesoul.in> # On fairphone-fp5 Link: https://lore.kernel.org/r/20260109-kodiak-lpass-tlmm-clocks-v1-1-746112687772@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: qrb2210-rb1: Add overlay for vision mezzanineLoic Poulain2-0/+71
This initial version includes support for OV9282 camera sensor. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20260108170550.359968-4-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: qrb2210-rb1: Add PM8008 nodeLoic Poulain1-0/+75
The PM8008 device is a dedicated camera PMIC integrating all the necessary camera power management features. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260108170550.359968-3-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-09arm64: dts: qcom: qcm2290: Add pin configuration for mclksLoic Poulain1-0/+28
Add pinctrl configuration for the four available camera master clocks. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20260108170550.359968-2-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07arm64: dts: qcom: qcs615: Drop IPA interconnectsKonrad Dybcio1-6/+0
In the same spirit as e.g. Commit 6314184be391 ("arm64: dts: qcom: sc8180x: Drop ipa-virt interconnect") drop the resources that should be taken care of through the clk-rpmh driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250627-topic-qcs615_icc_ipa-v1-1-dc47596cde69@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: qcs615-ride: Enable DisplayPortXiangxu Yin1-0/+30
Add DP connector node and configure MDSS DisplayPort controller for QCS615 Ride platform. Include PHY supply settings to support DP output. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251104-add-displayport-support-to-qcs615-devicetree-v7-4-e51669170a6f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: talos: Add DisplayPort and QMP USB3-DP PHYXiangxu Yin1-2/+113
Introduce DisplayPort controller node and associated QMP USB3-DP PHY for SM6150 SoC. Add data-lanes property to the DP endpoint and update clock assignments for proper DP integration. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251104-add-displayport-support-to-qcs615-devicetree-v7-3-e51669170a6f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: sm8750-qrd: Enable Iris codecKrzysztof Kozlowski1-0/+4
Enable on SM8750 QRD the Iris video codec for accelerated video encoding/decoding. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-3-97db1d1df3dd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: sm8750-mtp: Enable Iris codecKrzysztof Kozlowski1-0/+4
Enable on SM8750 MTP the Iris video codec for accelerated video encoding/decoding. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-2-97db1d1df3dd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: sm8750: Add Iris VPU v3.5Krzysztof Kozlowski1-0/+121
Add Iris video codec to SM8750 SoC, which comes with significantly different powering up sequence than previous SM8650, thus different clocks and resets. For consistency keep existing clock and clock-names naming, so the list shares common part. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-1-97db1d1df3dd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: Add The Fairphone (Gen. 6)Luca Weiss2-0/+791
Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based on the Milos/SM7635 SoC. Supported functionality as of this initial submission: * Debug UART * Regulators (PM7550, PM8550VS, PMR735B, PM8008) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * Power Button, Volume Keys, Switch * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Camera flash/torch LED * SD card * USB Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-9-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: Add initial Milos dtsiLuca Weiss1-0/+2633
Add a devicetree description for the Milos SoC, which is for example Snapdragon 7s Gen 3 (SM7635). Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-8-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: Add PMIV0104 PMICLuca Weiss1-0/+73
Add a dts for the PMIC used e.g. on devices with the Milos SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-7-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: Add PM7550 PMICLuca Weiss1-0/+67
Add a dts for the PMIC used e.g. with Milos SoC-based devices. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-6-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by defaultLuca Weiss10-0/+152
Keep the different PMIC definitions in pm8550vs.dtsi disabled by default, and only enable them in boards explicitly. This allows to support boards better which only have pm8550vs_c, like the Milos/SM7635-based Fairphone (Gen. 6). Note: I assume that at least some of these devices with PM8550VS also don't have _c, _d, _e and _g, but this patch is keeping the resulting devicetree the same as before this change, disabling them on boards that don't actually have those is out of scope for this patch. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-5-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-06dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6)Luca Weiss1-0/+5
Document the Milos-based The Fairphone (Gen. 6) smartphone. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-4-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.Sushrut Shree Trivedi1-0/+85
PCIe0 is routed to an m.2 E key connector on the mainboard for wifi attaches while PCIe1 routes to a standard PCIe x4 expansion slot. Hence, enable the PCIe0 and PCIe1 controller and phy-nodes. Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251128104928.4070050-7-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: qcs8300-ride: enable pcie1 interfaceZiyue Zhang1-0/+42
Add configurations in devicetree for PCIe1, board related gpios, PMIC regulators, etc for qcs8300-ride platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251128104928.4070050-6-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: qcs8300: enable pcie1Ziyue Zhang1-1/+192
Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s. Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251128104928.4070050-5-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: qcs8300-ride: enable pcie0 interfaceZiyue Zhang1-0/+42
Add configurations in devicetree for PCIe0, board related gpios, PMIC regulators, etc for qcs8300-ride board. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251128104928.4070050-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: qcs8300: enable pcie0Ziyue Zhang1-1/+180
Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251128104928.4070050-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: x1e80100: add TRNG nodeHarshal Dev1-0/+5
The x1e80100 SoC has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251223-trng_dt_binding_x1e80100-v4-2-5bfe781f9c7b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: sm8750: Fix BAM DMA probingKrzysztof Kozlowski1-0/+2
Bindings always required "qcom,num-ees" and "num-channels" properties, as reported by dtbs_check: sm8750-mtp.dtb: dma-controller@1dc4000 (qcom,bam-v1.7.4): 'anyOf' conditional failed, one must be fixed: 'qcom,powered-remotely' is a required property 'num-channels' is a required property 'qcom,num-ees' is a required property 'clocks' is a required property 'clock-names' is a required property However since commit 5068b5254812 ("dmaengine: qcom: bam_dma: Fix DT error handling for num-channels/ees") missing properties are actually fatal and BAM does not probe: bam-dma-engine 1dc4000.dma-controller: num-channels unspecified in dt bam-dma-engine 1dc4000.dma-controller: probe with driver bam-dma-engine failed with error -22 Fixes: eeb0f3e4ea67 ("arm64: dts: qcom: sm8750: Add QCrypto nodes") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251229115734.205744-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: monaco: add QCrypto nodeAbhinaba Rakshit1-0/+12
Add Qualcomm Crypto Engine device node for Monaco platform. QCE and Crypto DMA nodes patch was applied as part of commit a86d84409947 ("arm64: dts: qcom: qcs8300: add QCrypto nodes"), however was partially reverted by commit cdc117c40537 ("arm64: dts: qcom: qcs8300: Partially revert "arm64: dts: qcom: qcs8300: add QCrypto nodes"") due to compatible string being mismatched against schema. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251224-enable-qualcomm-crypto-engine-for-monaco-v3-1-6073430bbc13@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: lemans: add QCrypto nodeAbhinaba Rakshit1-0/+12
Add Qualcomm Crypto Engine device node for LeMans platform. QCE and Crypto DMA nodes patch was applied as part of the commit 7ff3da43ef44 ("arm64: dts: qcom: sa8775p: add QCrypto nodes"), however was partially reverted by commit 92979f12a201 ("arm64: dts: qcom: sa8775p: Partially revert "arm64: dts: qcom: sa8775p: add QCrypto nodes"") due to compatible-string being miss-matched against schema. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251224-enable-qualcomm-crypto-engine-for-lemans-v2-1-a707e3d38765@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-05arm64: dts: qcom: x1e80100-medion-sprchrgd-14-s1: correct firmware pathsDmitry Baryshkov1-6/+6
Per the agreement, the firmware paths (even for devices not supported in linux-firmware) should follow the SoC/Vendor/device pattern. Update firmware names for Medion SPRCHRGD 14 S1 to follow that pattern. Fixes: 8cf65490cdb0 ("arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1") Cc: Georg Gottleuber <ggo@tuxedocomputers.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251224-fix-medion-v1-1-305747dff79a@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-04-29 09:06:00 +0300