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| author | Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> | 2025-11-28 13:49:25 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-01-05 19:49:18 +0300 |
| commit | 33967eadb2153d92ea1de6e9c9ac8ade21c74d86 (patch) | |
| tree | c546c35fdeaedbcada0f1c0e2f9ec8851b944f66 | |
| parent | 46a7c01e7e9d296ba09bad579ae0277cfb558b24 (diff) | |
| download | linux-33967eadb2153d92ea1de6e9c9ac8ade21c74d86.tar.xz | |
arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
Add configurations in devicetree for PCIe0, board related gpios,
PMIC regulators, etc for qcs8300-ride board.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251128104928.4070050-4-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 4a8ac26846c6..e204dbd54f72 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -353,6 +353,25 @@ status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -398,6 +417,29 @@ }; &tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; |