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2026-01-15arm64: dts: renesas: rzg3e-smarc-som: Enable I3C supportTommaso Merciai1-0/+14
Enable I3C on RZ/G3E SMARC SoM. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/9d1cf2cdb1c11f24378404142e4c8aff680c6961.1763638659.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-12arm64: dts: renesas: Use lowercase hexKrzysztof Kozlowski11-186/+186
The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251223152358.152533-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-12arm64: dts: renesas: Use hyphens in node namesKrzysztof Kozlowski10-15/+15
DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251223152358.152533-3-krzysztof.kozlowski@oss.qualcomm.com [geert: Fix'em all] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-12arm/arm64: dts: renesas: Drop unused .dtsiRob Herring (Arm)14-614/+0
These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251212203226.458694-1-robh@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: rzt2h-n2h-evk-common: Use GPIO for SD0 write protectLad Prabhakar1-2/+2
Switch SD0 write-protect detection to a GPIO on the RZ/T2H and RZ/N2H EVKs. Both boards use a full-size SD card slot on the SD0 channel with a dedicated WP pin. The RZ/T2H and RZ/N2H SoCs use of_data_rcar_gen3, which sets MMC_CAP2_NO_WRITE_PROTECT and causes the core to ignore the WP signal unless a wp-gpios property is provided. Describe the WP pin as a GPIO to allow the MMC core to evaluate the write-protect status correctly. Fixes: d065453e5ee0 ("arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260106131319.643084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g057: Add CANFD nodeLad Prabhakar1-0/+60
Add CANFD node to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g056: Add CANFD nodeLad Prabhakar1-0/+60
Add CANFD node to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Enable CANFDLad Prabhakar1-0/+29
Enable CANFD channel 1, which is available on the CN35 connector. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable CANFDLad Prabhakar1-0/+21
Enable CANFD channel 0, which is available on the CN55 connector. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add CANFD nodeLad Prabhakar1-0/+31
Add support for the CANFD controller on the Renesas RZ/N2H Soc. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add CANFD nodeLad Prabhakar1-0/+31
Add support for the CANFD controller on the Renesas RZ/T2H Soc. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09Merge tag 'renesas-r9a09g077-dt-binding-defs-tag6' into renesas-dts-for-v6.20Geert Uytterhoeven2-0/+6
Renesas RZ/T2H and RZ/N2H PCLKCAN Clock DT Binding Definitions PCLKCAN Clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
2026-01-09arm64: dts: renesas: r9a09g057: Add RSCI nodesLad Prabhakar1-0/+220
Add RSCI nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251222164238.156985-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g056: Add RSCI nodesLad Prabhakar1-0/+220
Add RSCI nodes to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251222164238.156985-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add GPIO keysCosmin Tanislav1-0/+30
The Renesas RZ/N2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keysCosmin Tanislav1-0/+33
The Renesas RZ/T2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add GPIO IRQ supportCosmin Tanislav1-0/+3
The Renesas RZ/N2H (R9A09G087) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add GPIO IRQ supportCosmin Tanislav1-0/+3
The Renesas RZ/T2H (R9A09G077) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add TSU and thermal zones supportCosmin Tanislav1-0/+46
The Renesas RZ/N2H (R9A09G087) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-10-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add TSU and thermal zones supportCosmin Tanislav1-0/+46
The Renesas RZ/T2H (R9A09G077) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add OPP tableCosmin Tanislav1-0/+19
Add OPP table for RZ/N2H SoC. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add OPP tableCosmin Tanislav1-0/+19
Add OPP table for RZ/T2H SoC. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-08riscv: dts: renesas: r9a07g043f: Move interrupt-parent to top nodeGeert Uytterhoeven1-1/+2
Move the "interrupt-parent = <&plic>" property from the soc node to the top node, for consistency with arch/arm64/boot/dts/renesas/r9a07g043u.dtsi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/97d3d70e42832f4ffa3888bec792b692a7ab700f.1767719409.git.geert+renesas@glider.be
2026-01-08dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN IDLad Prabhakar2-0/+2
Add PCLKCAN ID for CANFD to both R9A09G077 and R9A09G087 SoCs. This definition is required for describing CANFD device in DT. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224165049.3384870-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a779h0: Add WWDT nodesWolfram Sang1-0/+112
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215034715.3406-14-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a779g0: Add WWDT nodesWolfram Sang1-0/+112
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215034715.3406-13-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a779f0: Add WWDT nodesWolfram Sang1-0/+160
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215034715.3406-12-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a779a0: Add WWDT nodesWolfram Sang1-0/+160
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215034715.3406-11-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a77980: Add WWDT nodesWolfram Sang1-0/+80
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215034715.3406-10-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a77970: Add WWDT nodesWolfram Sang1-0/+32
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215034715.3406-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: condor/v3hsk: Mark SWDT as reservedWolfram Sang2-0/+10
This watchdog can't be used with Linux because the firmware needs it on R-Car V3H boards. Sadly, it doesn't mark the node as reserved, so this is added manually here. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215031318.2219-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r8a77980: Add SWDT nodeWolfram Sang1-0/+9
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251215031318.2219-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add TSU nodesOvidiu Panait1-0/+75
The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251209091115.8541-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g087: Add DMAC supportCosmin Tanislav1-0/+90
The Renesas RZ/N2H (R9A09G087) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205151254.2970669-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g077: Add DMAC supportCosmin Tanislav1-0/+90
The Renesas RZ/T2H (R9A09G077) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205151254.2970669-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g087: Add ICU supportCosmin Tanislav1-0/+73
The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g077: Add ICU supportCosmin Tanislav1-0/+73
The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodesBiju Das3-0/+69
Enable device rsci{2,4,9} nodes for the RZ/G3E SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251129185203.380002-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: renesas-smarc2: Move aliases to board DTSBiju Das2-6/+6
SMARC2 board dtsi is common for multiple SoCs. So Move aliases to board DTS as SoC may have different IPs for a given alias. eg: RZ/G3S does not have RSCI interface. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251129185203.380002-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g047: Add RSCI nodesBiju Das1-0/+220
Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251129185203.380002-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05ARM: dts: renesas: r9a06g032: Add Ethernet switch interruptsGeert Uytterhoeven1-0/+6
The Ethernet switch device node still lacks interrupts. Add them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/53d45eed3709cba589a4ef3e9ad198d7e44fd9a5.1764249063.git.geert+renesas@glider.be
2026-01-05arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button supportLad Prabhakar1-0/+13
Add support for the NMI connected user pushbutton on the RZ/V2N EVK. The button is wired to the SoC NMI input and can be used to wake the system from low-power states. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add RSPI nodesLad Prabhakar1-0/+63
Add nodes for the RSPI IPs found in the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add DMAC nodesLad Prabhakar1-0/+165
Add nodes for the DMAC IPs found on the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add ICU nodeLad Prabhakar1-0/+92
Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2N SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g047e57-smarc: Remove duplicate SW_LCD_ENGeert Uytterhoeven1-1/+0
SW_LCD_EN is defined twice. Fixes: 9e95446b0cf93a91 ("arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/1f93558c62f4461f50935644ec831a7d2cb52630.1764089463.git.geert+renesas@glider.be
2026-01-05arm64: dts: renesas: r9a09g087: Add SPI nodesCosmin Tanislav1-0/+72
Add support for the four SPI controllers on the Renesas RZ/N2H Soc. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119161434.595677-14-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g077: Add SPI nodesCosmin Tanislav1-0/+72
Add support for the four SPI controllers on the Renesas RZ/T2H Soc. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119161434.595677-13-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: rzg3s-smarc: Enable PCIeClaudiu Beznea1-0/+11
The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe support. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251119143523.977085-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clockClaudiu Beznea1-0/+5
Versa3 clock generator available on RZ/G3S SMARC Module provides the reference clock for SoC PCIe interface. Update the device tree to reflect this connection. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251119143523.977085-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-03 05:14:01 +0300