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| author | Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> | 2025-11-26 16:03:54 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-01-09 13:46:46 +0300 |
| commit | ffcc240e3680e77d36c99026f5da81553d559246 (patch) | |
| tree | 2fe80706402447b093ad1ca3b2658f19c974a517 | |
| parent | 98aa86525051bbb974818cd27f9a6fbaf255975b (diff) | |
| download | linux-ffcc240e3680e77d36c99026f5da81553d559246.tar.xz | |
arm64: dts: renesas: r9a09g087: Add OPP table
Add OPP table for RZ/N2H SoC.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251126130356.2768625-8-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index f3225694b4cb..a6a558e0ccd9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +45,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +55,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +65,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { |