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AmlCreateRootNode() calls AmlDeleteRootNode() when SDT header
allocation fails. However, AmlDeleteRootNode() rejects a NULL header
and returns without freeing the root node, leaking the node allocation.
Allow AmlDeleteRootNode() to handle a NULL SDT header and always free
the root node.
Signed-off-by: Amrathesh <amrathesh@arm.com>
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AmlCreateDataNode() calls AmlDeleteDataNode() when buffer allocation
fails. However, AmlDeleteDataNode() rejects a NULL buffer and returns
without freeing the data node, leaking the node allocation.
Allow AmlDeleteDataNode() to handle a NULL buffer and always free the
data node.
Signed-off-by: Amrathesh <amrathesh@arm.com>
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AmlSetFixedArgument() accepts an index equal to the fixed argument count.
The count is an exclusive upper bound, so this permits an out-of-bounds
write to the FixedArgs array.
Require the index to be strictly less than the fixed argument count.
Signed-off-by: Amrathesh <amrathesh@arm.com>
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AmlSerializeTree uses a reversed buffer size comparison. As a result, it
returns success without serializing when the buffer is larger than needed
and attempts serialization when the buffer is too small.
Return EFI_BUFFER_TOO_SMALL when Buffer is NULL or the supplied buffer is
too small, and always report the required size. Update
AmlSerializeDefinitionBlock to handle the expected size query status.
Signed-off-by: Amrathesh <amrathesh@arm.com>
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Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Add a common Error Record Serialization Table (ERST) generator based on
the ACPI 6.6 definition. Introduce an architecture-common Configuration
Manager object to provide serialization instruction entries.
Validate actions, instructions, flags, register masks, action grouping,
and GOTO targets before generating the table.
Signed-off-by: Amrathesh <amrathesh@arm.com>
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Add a common Boot Error Record Table (BERT) generator based on the
ACPI 6.6 definition. Introduce an architecture-common Configuration
Manager object that provides the boot error region address and length.
Signed-off-by: Amrathesh <amrathesh@arm.com>
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Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Several fields are missing from the GICv5 Configuration Manager object
parsers, including those used for SRAT.
Add the missing fields.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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To support SPCR with GicV5, check GiCv5 SPI IRQ ranges too.
And cleanup for ifdef for ARM specific validation with the Arch
specific function to validate serial port information.
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
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Generate GICv5 related information in IORT table.
Continuous-integration-options: PatchCheck.ignore-multi-package
Co-Developed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
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Generate GICv5 related information in MADT table.
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
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Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Extend the CMN Configuration Manager object with an implementation type
and optional root-node region length.
Map the implementation type to the ACPI hardware IDs for CMN-600,
CMN-650, CMN-700 and CMN-S3. Apply CMN-600-specific address restrictions
only when the CMN-600 implementation type is selected.
Rename the CMN-600 generator, identifiers and files to reflect support
for multiple CMN implementations.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenEqual() to create an AML LEqual expression from two
supplied operands.
Use the existing AML_METHOD_PARAM representation for integer, method
argument, and local variable operands. The generated equality expression
can be used as a predicate by control-flow objects.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenIf() to create an AML If object from a supplied
predicate node.
The API takes ownership of the predicate and returns an If node to
which executable statements can subsequently be appended.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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AmlSetFixedArgument() attaches NewNode to an AML object but does not
currently verify that the node is detached. Passing an already attached
node could leave the AML tree in an inconsistent state.
Require non-NULL argument nodes to be detached before attaching them.
Continue accepting NULL because callers use it to clear a fixed
argument.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Use AmlComputePkgLength() when calculating the package lengths for
Device, ThermalZone, and Scope objects.
The package-length encoding width is included in the encoded length and
can itself increase when that width is added. AmlComputePkgLength()
handles this boundary condition correctly.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenStoreToName() to create an AML Store operation with a
typed source operand and a named target.
Support integer, method argument and local variable sources using the
AML_METHOD_PARAM representation. Append the generated Store node to an
optional parent object.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenFieldElemNamed() to create a named element within an AML
Field list.
The API validates the supplied NameSeg and field length, encodes the
length using the AML FieldPkgLen format, and appends the resulting
NamedField node to its parent Field object.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenFieldElemReserved() to create an AML ReservedField
element and append it to a Field list.
The API accepts the reserved range length in bits and validates that
the parent supports a Field list. ReservedField elements describe
unnamed gaps in Field declarations and can be used when translating
ASL Offset() declarations.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Validate that the package length passed to AmlCreateObjectNode() fits
within the 28-bit limit defined by the AML package-length encoding.
Perform the validation centrally so that it applies consistently to all
callers.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenField() to create an empty AML Field object associated
with an OperationRegion.
Expose access type, lock rule, and update rule through typed public
enumerations and encode them in the Field flags byte. The generated
Field node can be attached directly to a parent or returned so that
field elements can subsequently be appended.
For example, the API can generate:
Field (REG0, DWordAcc, NoLock, Preserve)
{
}
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add AmlCodeGenOperationRegion() to create an AML OperationRegion
object from a region name, address space, integer offset, and integer
length.
The API creates the OperationRegion object and populates its four fixed
AML operands:
- RegionName
- RegionSpace
- RegionOffset
- RegionLength
RegionOffset and RegionLength are encoded using the smallest suitable
AML integer representation. The generated node can either be attached
directly to a supplied parent or returned to the caller for later use.
For example, the API can generate an object equivalent to:
OperationRegion (
REG0,
SystemMemory,
RegionOffset,
RegionLength
)
This provides generators with a reusable way to describe register
regions without relying on a precompiled ASL template.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Allow AmlCodeGenNotifyNode() to attach a Notify object to any suitable
parent node.
This enables Notify objects to be generated within nested AML scopes,
for example:
Method (_EVT, 1, Serialized)
{
If (LEqual (Arg0, EventId))
{
Notify (\_SB.RAS0, Value)
}
}
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Make AmlCodeGenNotify() public and declare it in AmlLib.h. Add the new
API to the CodeGen documentation group.
Callers currently cannot append an individual Notify operation while
incrementally constructing a method body.
For example, this enables generators to construct _EVT methods
containing conditional register writes and device notifications.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Ensure AmlCodeGenNotifyNode() consistently owns its operand nodes after
successful input validation.
Track operands as they are attached to the Notify object so error
handling deletes unattached operands directly and attached operands
through their parent. Clear the caller references after ownership is
transferred to prevent double deletion on failure.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Rename the DMC-620 PMU generator and its Configuration Manager objects
to remove the DMC-620-specific naming.
Update the generator ID, library paths, parser definitions and associated
documentation to use generic DMC PMU terminology.
Signed-off-by: Varshit Pandya <Varshit.Pandya@arm.com>
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Add SMBIOS Type 42 related CM object structures
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add MSCT maximum physical address configuration object and
update parser to handle the new object type.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Define TableHelperLib field parsers for all LoongArch64 Configuration
Manager objects. Also dispatch the LoongArch64 namespace through
ParseCmObjDesc() so CM debug output can print these objects instead of
reporting the namespace as unsupported.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
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To generate Arm Performance Moniteroing Unit Table (APMT), introduce
Arm coresight PMU CM object.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add missing CmRiscVProcessorSpecificBlockInfo Parser.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add missing CmX64ProcessorSpecificBlockInfo Parser.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add missing CmArchCommonProcessorSpecificBlockInfo Parser.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add missing CmArmProcessorSpecificBlockInfo Parser.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add missing CmArmProcessorSpecificSubDataArchInfo parser.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add a new StaToken field to CM_ARCH_COMMON_PROC_HIERARCHY_INFO
CmObj, allowing to describe the ASL "_STA" value the processor
or processor container should return.
CM_X64_LOCAL_APIC_X2APIC_INFO.StaToken already allows to reference
a StaToken from a X2APIC CmObj. If ProcHierarchy objects are used,
the SSDT CPU topology table will be generated using the X2APIC
objects, so the new field should not collide with the new one.
Add a note to CM_X64_LOCAL_APIC_X2APIC_INFO.StaToken
to handle this case.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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In AmlCodeGenRdInterrupt(), the IRQ list was copied directly into an
EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR structure allocated on the stack.
Since the structure only contains storage for the first interrupt entry,
copying multiple IRQs would write beyond the allocated buffer and corrupt
the stack.
Fix this issue by allocating the descriptor dynamically with sufficient
space to accommodate the entire IRQ list. This ensures all interrupt entries
are copied safely without overwriting adjacent stack memory.
Signed-off-by: Tuan Phan <tuan.phan@oss.qualcomm.com>
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Add support for generating AML methods that return a buffer through the
new AmlCodeGenMethodRetBuffer() API.
Signed-off-by: Tuan Phan <tuan.phan@oss.qualcomm.com>
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There is currently no API available for generating AML methods without
a return value. This change exports the AmlCodeGenMethod API so it can
be used to create non-returning methods when required.
Signed-off-by: Tuan Phan <tuan.phan@oss.qualcomm.com>
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Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Add the Configuration Manager objects required to describe SMBIOS
Additional Information (Type 40) structures.
The top-level object references a list of Additional Information entries.
Each entry identifies a field in an existing SMBIOS structure and
references a typed value object containing the additional data.
Define the maximum value buffer size from the SMBIOS Type 40 formatted
length limit and add parsers for the new CM objects.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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Add EArchCommonObjSystemInfo to ArchCommonNameSpaceObjects.h and a
corresponding parser entry in ConfigurationManagerObjectParser.c.
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
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Add the following functions to the AmlResourceDataApi:
- AmlUpdateRdDWord()
- AmlUpdateRdWord()
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Some combination of fields of Rd Address Space descriptors
are not valid. Check them when updating a Rd Address Space
descriptor.
Cf. ACPI 6.4 Table 6.44:
"Valid Combination of Address Space Descriptor Fields"
Also check that the input length is not 0 to avoid
potential integer underflow.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Move the CheckAddressSpaceFields() function to AmlUtility.c
to allow other files to re-use it.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Add support for generating SMBIOS Type 37 Memory Channel structures from
Configuration Manager data.
Introduce the Memory Channel CM object and the associated Memory Channel
Device CM object. The channel object describes the Type 37 fixed fields,
including channel type, maximum channel load, memory device count, and the
token for the device-list object. The device-list object describes each
memory device attached to the channel using a device load and a Type 17
Memory Device CM token.
Add parser entries for both CM objects and register the Type 37 generator in
the DynamicTablesPkg DSC so it is available through the SMBIOS table factory.
The Type 37 generator builds one SMBIOS record per Memory Channel CM object.
For each channel, it retrieves the referenced Memory Channel Device list,
validates the channel type, maximum channel load, device count, device load,
and device tokens, resolves each referenced Type 17 CM token to an SMBIOS
handle, and emits the variable-length MemoryDevice array in the Type 37
record.
This allows platforms to describe memory channels and link them to generated
Type 17 Memory Device records through CM tokens instead of hard-coded SMBIOS
handles.
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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