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9 hoursDynamicTablesPkg: Add SMBIOS System Power Supply generatorHEADmasterGirish Mahadevan3-0/+599
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
9 hoursDynamicTablesPkg: Add System Power Supply CM object and parserGirish Mahadevan2-0/+71
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
18 hoursDynamicTablesPkg: Safely populate AML definition block IDsVarshitPandya2-7/+50
Bound the number of bytes copied into the fixed-width ACPI table signature, OEM ID, and OEM table ID fields. Pad shorter identifiers with spaces. This prevents reads beyond shorter input strings while continuing to support fixed-width inputs without NULL terminators. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
18 hoursDynamicTablesPkg: Fix DMC PMU interrupt flag handlingVarshitPandya1-6/+24
Interpret the DMC PMU interrupt flags using the ACPI Extended Interrupt Descriptor masks. Validate the consumer, trigger mode, and polarity attributes, and propagate all interrupt attributes, including sharability, when generating the AML resource. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Add cache topology parserPierre Gondois8-0/+1245
Add a ParseCacheInfo() function, parsing CPU cache information from Device Tree and creating CM_ARCH_COMMON_CACHE_INFO objects. Parse: - L1 cache information directly from CPU cache properties - shared caches from "next-level-cache" DT nodes Track cache sharing through CPU masks and attach cache references to the deepest matching processor hierarchy node. The processor hierarchy objects must be added after the cache information is parsed as cache references are stored in ProcHierarchy objects. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Populate additional topology infoPierre Gondois6-21/+313
Add topology utility functions to manipulate CPU masks associated with processor hierarchy nodes. Rework the topology parser context to keep: - the list of CPU DT nodes - per-node CPU masks - parent indexes - node depth Populate these fields while creating the processor hierarchy. This data will be used in a later patch to attach cache objects to the proper hierarchy nodes. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Parse ProcessorId from SoC IDPierre Gondois5-1/+123
Populate processor hierarchy ProcessorId fields from the SoC. To allow different architectures to implement flavours of GetSocId(), introduce ArchUtility.c/h files which aim to contain architecture-specific implementations of generic code. A dependency over ArmSmcccSocIdLib is also added. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Add topology parserPierre Gondois7-0/+806
Add a TopologyInfoParser() function, parsing the "/cpus" node and the optional "cpu-map" hierarchy to create CM_ARCH_COMMON_PROC_HIERARCHY_INFO objects. When no "cpu-map" node is present, create a flat topology with a single package node containing all CPUs. Add the corresponding FDT HwInfo object identifier and hook the new parser in ArmFdtHwInfoParser. The parser must be called after the GIC parsers as leaf topology nodes point to GicC objects. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Assign CPU tokens to GICC objectsPierre Gondois3-7/+75
Create Tokens identifying Gic CPU interfaces. The Configuration Manager relies on PROC_HIERARCHY_INFO structures to represent the CPU topology. These objects have fields: - ParentToken: Token identifying the parent of this struct - AcpiIdObjectToken: Token identifying a Gic CPU interface (for arm) The Gic CPU interface information and topology information will be parsed in 2 different files. The same token will have to be generated for: - a GicC object - the ProcHierarchy object pointing to this GicC object Also add missing documentation in CpusNodeParser() and add a CM_ABSTRACT_TOKEN_ID_MASK macro. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Add modulo check to AddMultipleCmObj()Pierre Gondois1-1/+2
Following the addition of AddMultipleCmObjWithToken(), add a check regarding the (Size % Count) to AddMultipleCmObj(). Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Add AddMultipleCmObjWithToken()Pierre Gondois2-2/+103
Add a AddMultipleCmObjWithToken() function, allowing to add multiple CmObj with their associated Token. This function will be used in a later patch to add GicC CmObj with specific Token. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Add IsCpuDeviceNode()Pierre Gondois3-14/+72
Add a IsCpuDeviceNode() function, identifying whether a FDT node is describing a CPU device. The function will be used in a later patch to parse the CPU topology. Use the new function in the GicC parser as it is more accurate/restrictive than identifying "cpu" nodes by only reading the node name. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Add FdtNodeHasNameEx()Pierre Gondois2-1/+101
Add a FdtNodeHasNameEx() function, checking node names following the convention where an Id is added at the end of the name. E.g. "socketN", "clusterN", "coreN", "threadN". This prepares the addition of topology/cache parsers. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Export FdtCountCondNodeInBranch()Pierre Gondois2-1/+30
Export FdtCountCondNodeInBranch(). The function will be used in a later patch to count the number of "cpu" nodes in order to parse the CPU topology. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg/HwInfoParser: Export FdtNodeHasName()Pierre Gondois2-1/+18
Export FdtNodeHasName(). The function will be used in a later patch to find "thread" nodes while parsing the CPU topology. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
30 hoursDynamicTablesPkg: Extract token definitions to AbstractToken.hPierre Gondois2-48/+69
Move the Abstract Token related definitions to a separate file in prevision of the addition of new definitions. No functional change. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
31 hoursDynamicTablesPkg: Add SMBIOS TPM Device generatorGirish Mahadevan4-2/+424
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
31 hoursDynamicTablesPkg: Add TPM Device CM object and parserGirish Mahadevan5-34/+92
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
2 daysDynamicTablesPkg/FdtHwInfoParserLib: Fix serial access size parsingDjordje Nedic1-5/+17
Previously, access size values were taken as-is, instead of mapped to ACPI defines. This made for incorrect parsing of DWORD and QWORD access sizes. Signed-off-by: Djordje Nedic <djordje.nedic@nextsilicon.com>
2 daysDynamicTablesPkg/AcpiSpcrLib: Accept RISC-V interrupt typeDjordje Nedic1-4/+8
The SPCR generator excludes the standard RISC-V PLIC/APLIC interrupt type from its valid interrupt mask. A platform supplying this type through EArchCommonObjSpcrInfo is consequently rejected with EFI_INVALID_PARAMETER. Include the RISC-V interrupt type in the valid mask. Like GIC, require it to be used on its own. Leave existing interrupt combinations, reserved-bit validation and platform defaults unchanged. Signed-off-by: Djordje Nedic <djordje.nedic@nextsilicon.com>
6 daysDynamicTablesPkg/AcpiFadtLib: Preserve platform flags on Arm and RISC-VDjordje Nedic2-2/+2
BuildFadtTable() adds platform-provided fixed-feature flags before calling FadtArchUpdate(). The Arm and RISC-V implementations assign Fadt->Flags, discarding the flags already added by the platform. Use bitwise OR assignment to add architecture defaults without overwriting the existing flags. Leave the generation order, validation masks, ACPI revision handling, and architecture defaults unchanged. Signed-off-by: Djordje Nedic <djordje.nedic@nextsilicon.com>
8 daysDynamicTablesPkg/AmlLib: Fix root node cleanup leakAmrathesh1-3/+0
AmlCreateRootNode() calls AmlDeleteRootNode() when SDT header allocation fails. However, AmlDeleteRootNode() rejects a NULL header and returns without freeing the root node, leaking the node allocation. Allow AmlDeleteRootNode() to handle a NULL SDT header and always free the root node. Signed-off-by: Amrathesh <amrathesh@arm.com>
8 daysDynamicTablesPkg/AmlLib: Fix data node cleanup leakAmrathesh1-4/+0
AmlCreateDataNode() calls AmlDeleteDataNode() when buffer allocation fails. However, AmlDeleteDataNode() rejects a NULL buffer and returns without freeing the data node, leaking the node allocation. Allow AmlDeleteDataNode() to handle a NULL buffer and always free the data node. Signed-off-by: Amrathesh <amrathesh@arm.com>
8 daysDynamicTablesPkg/AmlLib: Fix fixed argument bounds checkAmrathesh1-1/+1
AmlSetFixedArgument() accepts an index equal to the fixed argument count. The count is an exclusive upper bound, so this permits an out-of-bounds write to the FixedArgs array. Require the index to be strictly less than the fixed argument count. Signed-off-by: Amrathesh <amrathesh@arm.com>
8 daysDynamicTablesPkg/AmlLib: Fix serialization buffer size handlingAmrathesh2-9/+11
AmlSerializeTree uses a reversed buffer size comparison. As a result, it returns success without serializing when the buffer is larger than needed and attempts serialization when the buffer is too small. Return EFI_BUFFER_TOO_SMALL when Buffer is NULL or the supplied buffer is too small, and always report the required size. Update AmlSerializeDefinitionBlock to handle the expected size query status. Signed-off-by: Amrathesh <amrathesh@arm.com>
8 daysDynamicTablesPkg: Add SMBIOS IPMI Device generatorGirish Mahadevan3-0/+371
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
8 daysDynamicTablesPkg: Add IPMI Device CM object and parserGirish Mahadevan2-0/+47
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
13 daysDynamicTablesPkg: Add ACPI ERST table generatorAmrathesh8-0/+601
Add a common Error Record Serialization Table (ERST) generator based on the ACPI 6.6 definition. Introduce an architecture-common Configuration Manager object to provide serialization instruction entries. Validate actions, instructions, flags, register masks, action grouping, and GOTO targets before generating the table. Signed-off-by: Amrathesh <amrathesh@arm.com>
14 daysDynamicTablesPkg: Add ACPI BERT table generatorAmrathesh8-0/+338
Add a common Boot Error Record Table (BERT) generator based on the ACPI 6.6 definition. Introduce an architecture-common Configuration Manager object that provides the boot error region address and length. Signed-off-by: Amrathesh <amrathesh@arm.com>
14 daysDynamicTablesPkg: Fix ACPI ID documentationAmrathesh2-34/+37
Correct the Arch Common object ID comments following the EINJ object. Also document the existing HMAT, APMT, and MSCT standard ACPI table generator IDs. Signed-off-by: Amrathesh <amrathesh@arm.com>
14 daysDynamicTablesPkg: Add SMBIOS Onboard Devices generatorGirish Mahadevan3-0/+454
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
14 daysDynamicTablesPkg: Add Onboard Device CM object and parserGirish Mahadevan2-0/+43
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
2026-09-16DynamicTablesPkg: Library: fix wrong iteration ITS affinity in SRATsecurity-advisory/cve-2026-92258/advisoryYeoreum Yun1-1/+2
For GicV5 ITS, it should be iterated with GicItsV5Info not GicItsInfo in SratGenerator. Fix wrong iteration. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
2026-09-16DynamicTablesPkg: Library: fix IWB node device index in IORT generatorYeoreum Yun3-8/+23
Up to 16 IWB devices can currently be created dynamically. However, the device name is derived from GicIwbId, which causes problems when GicIwbId is greater than 16. Use a separate index to generate the device name instead. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
2026-09-15DynamicTablesPkg: fix missing field relevant GiCv5 CM object for parsersYeoreum Yun1-10/+16
Several fields are missing from the GICv5 Configuration Manager object parsers, including those used for SRAT. Add the missing fields. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
2026-09-15DynamicTablesPkg/HwInfoParser: Fix FdtResolveInterrupt() on absent propertyPierre Gondois1-2/+1
FdtResolveInterrupt() might be called on a node with an absent "interrupts" property. In such case, the function should: - not assert - return EFI_NOT_FOUND This ASSERT is triggered when running ArmVirtKvmtool, when searching for a GSIV maintenance interrupt. Fixes: b377584b344a ("DynamicTablesPkg/HwInfoParser: Add FdtResolveInterrupt()") Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
2026-09-15DynamicTablesPkg: MadtGenerator: make GICD info as optionLevi Yun1-15/+32
GICD information is not a mandatory in the platform where use the GicV5 interrupt controller. Therefore, make GICD information as optional one. Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
2026-09-15DynamicTablesPkg: SsdtSerialPortFixupLib: Add GICv5 IRQ ranges to IRQ checkSarah Walker7-22/+178
To support SPCR with GicV5, check GiCv5 SPI IRQ ranges too. And cleanup for ifdef for ARM specific validation with the Arch specific function to validate serial port information. Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
2026-09-15DynamicTablesPkg,MdePkg: generate IORT table for GICv5Sarah Walker8-31/+873
Generate GICv5 related information in IORT table. Continuous-integration-options: PatchCheck.ignore-multi-package Co-Developed-by: Yeoreum Yun <yeoreum.yun@arm.com> Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
2026-09-15DynamicTablesPkg,MdePkg: validate number of ItsGroupCount in IORTYeoreum Yun1-1/+12
Since the IORT specification version E.g[0], Number of ITS node (a.k.a ITS Group node) must be "1". To ensure compliance with the specification, add a sanity check for the number of ITS Group nodes. Link: https://developer.arm.com/documentation/den0049/latest [0] Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
2026-09-15DynamicTablesPkg: generate SRAT table for GICv5Sarah Walker3-20/+179
Generate GICv5 related information in SRAT table. Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
2026-09-15DynamicTablesPkg: generate MADT table for GICv5Sarah Walker3-35/+493
Generate GICv5 related information in MADT table. Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
2026-09-15DynamicTablesPkg: Smbios System Boot Information (Type 32)Girish Mahadevan3-0/+321
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
2026-09-15DynamicTablesPkg: Add System Boot CM object and parserGirish Mahadevan2-0/+23
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
2026-09-14DynamicTablesPkg: Smbios Firmware Language Information (Type 13)Girish Mahadevan3-0/+475
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
2026-09-14DynamicTablesPkg: Add BIOS Language CM object and parserGirish Mahadevan2-0/+50
Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com>
2026-09-11DynamicTablesPkg/HwInfoParser: Remove IRQ helper macrosPierre Gondois1-39/+0
The following IRQ helper macros are now unused: - GET_DT_REG_ADDRESS_OFFSET() - GET_DT_REG_SIZE_OFFSET() Remove them. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
2026-09-11DynamicTablesPkg/HwInfoParser: Add FdtGetTranslatedReg()Pierre Gondois10-13/+292
The Devicetree Specification [1] defines the "ranges" property. """ The ranges property provides a means of defining a mapping or translation between the address space of the bus (the child address space) and the address space of the bus node’s parent (the parent address space). """ Add a FdtGetTranslatedReg() function, reading the "reg" property of a node and translating the base address through the "ranges" properties present in the node hierarchy. Make use of FdtGetTranslatedReg() wherever relevant. This allows to handle the presence of "ranges" property in a node hierarchy by default. [1] Spec. v0.4, s2.3.8 ranges Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
2026-09-11DynamicTablesPkg/HwInfoParser: Add FdtGetReg() helperPierre Gondois10-232/+290
Add a FdtGetReg() helper to fetch the "reg" property of a node. Use the newly introduce helper wherever relevant. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
2026-09-11DynamicTablesPkg/HwInfoParser: Add FdtResolveInterrupt()Pierre Gondois5-136/+430
The Devicetree Specification [1] defines the concept of interrupt mapping, interrupt domain, interrupt nexus and interrupt controller. An interrupt property might need to be translated through an interrupt nexus to obtain the interrupt type, id, flags. Add a FdtResolveInterrupt() function, resolving an interrupt property through interrupt nexuses until reaching the interrupt-controller node. Make use of FdtResolveInterrupt() wherever relevant. This allows to handle the presence of interrupt nexus by default. [1] Spec. v0.4, s2.4 Interrupts and Interrupt Mapping Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 12:41:15 +0300