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Change the legacy VGA range (0xA0000-0xC0000) from Uncacheable to
WriteThrough. Guard the TOM1-derived WriteBack MTRR range against
TOM1 <= 1MB instead of unconditionally subtracting, avoiding a UINT64
underflow into a huge bogus range. Explicitly mark the ROM3 SPI/flash
MMIO window (read from the FCH PMIOA base-address registers) as
Uncacheable in SetCacheMtrrAfterEndOfPei(), which was previously left
with whatever attribute the default MTRR left it in.
Add the missing FCH_PMIOA_REG64 (AcpiPmTmrBlk) register offset to
AgesaModulePkg's FchRegistersCommon.h - this package's copy is a
hand-curated subset of AGESA's full register header and only had
FCH_PMIOA_REG60 defined, so SetCacheMtrrAfterEndOfPei()'s new ROM3
base-address read failed to build.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Drop the deprecated SPI drivers, put BoardSpiConfig and
EspiNorFlash, and add the SpiFvb variable
and RDE response drivers. Rework SpiHcPlatformLib so the DXE and SMM
instances share one hardware path, and drop the null instance.
Which are now part of edk2 repo.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Build the ROM Armor SPI host-controller library for DXE and SMM.
Platforms select it by setting ROM_ARMOR_ENABLED to TRUE, which maps
SpiHcPlatformLib to these instances. The default remains FALSE, so the
existing null SpiHcPlatformLib mapping is unchanged.
Supporting changes:
- Add PcdRomArmorWhitelistEnable to AgesaCommonModulePkg.
- Map a null AmdEmulationAutoDetectLib for DXE and DXE_SMM.
- Drop the local mFchDevicePath definition. AmdSpiDevicePaths.h already
provides that object, and a second definition failed the build.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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ConfigurationManagerDxe (DXE_DRIVER):
Implements EDKII_CONFIGURATION_MANAGER_PROTOCOL. Populates a static
repository (EDKII_PLATFORM_REPOSITORY_INFO) with CM objects for:
FACS, FADT, HPET, WSMT, SPMI, MCFG, MADT. Updates MADT from
EFI_MP_SERVICES_PROTOCOL, MCFG from PciSegmentInfoLib, and HPET from
hardware detection. Calls UpdatePlatformCmInfo() for SoC-specific data.
NULL DXE libraries (linked into ConfigurationManagerDxe via DSC override):
AcpiDsdtLib — installs pre-compiled Dsdt.asl as the platform DSDT
AcpiSsdtCpuTopologyLib — generates CPU topology SSDT from MP-Services data
AcpiSsdtEspiUartLib — conditionally installs eSPI UART SSDT
AcpiSsdtPciLib — generates PCIe root bridge, USB, and system device SSDTs
AcpiSsdtSerialLib — generates FCH UART SSDT (MMIO + legacy I/O paths)
SampleCmPlatOverrideLib — demonstrates CM table override pattern for IBVs
Required fixups:
- Add 15 new PCDs to AmdPlatformPkg.dec [PcdsFixedAtBuild]:
PcdAcpiSsdtSerialSkipOnSimNow, 9 x PcdAmdAcpi*OemTableId,
PcdAmdNumaCcdOrder, 4 x PcdLegacyUartIrq0x*.
- Add PcdUsePlatformAcpi and PcdAmdIdsUartBaudRate to AgesaPkg.dec.
- Add PcdAmdSimNowEn to AmdCpmPkg.dec.
- Add FCH_AL2AHBx20_LEGACY_UART_IO_ENABLE to FchRegistersCommon.h.
- Add AmdConfigurationManager.h to AmdPlatformPkg/Include/.
- Extend AmdPlatformSocLib.h/DxePlatformSocLibNull.c with the
LinkHotplug/EcrcSupport fields and GetPcieEcrcSupport()/
UpdatePlatformCmInfo() hooks actually consumed by this module.
- Map LocalApicLib and PciSegmentInfoLib for DXE_DRIVER in the DSC, and
wire all 7 modules into AmdPlatformPkg.dsc/dsc.inc [Components.X64].
- Add missing SPDX-License-Identifier tags to 4 vendor .asl/.asi files.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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AmdPostCodeLibNull is a no-op AmdPostCodeLib instance so AGESA modules
that call LibAmdPostCode can link when a real post-code backend is not
present. ACCESS_WIDTH is defined in AMD.h, AmdPostCodeLib.h declares
LibAmdPostCode, and AmdPlatformPkg.dsc maps AmdPostCodeLib to the NULL
instance.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Update of AMD EDKII Platform Code for 5th Generation EPYC Processors (formerly Turin).
This sample platform code was tested to work with the Turin 1.0.0.7 AGESA PI package, which is available from AMD under license and NDA.
Signed-off-by: Paul Grimes <paul.grimes@amd.com>
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Update of AMD EDKII Platform Code for 5th Generation EPYC Processors (formerly Turin).
This sample platform code was tested to work with the Turin 1.0.0.5 AGESA PI package, which is available from AMD under license and NDA.
Signed-off-by: Paul Grimes <paul.grimes@amd.com>
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Initial commit of AMD EDKII Platform Code for 5th Generation EPYC Processors (formerly Turin).
This sample platform code was tested to work with the Turin 1.0.0.4 AGESA PI package, which is available from AMD under license and NDA.
Signed-off-by: Paul Grimes <paul.grimes@amd.com>
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BZ#: 4777
Initial commit of AMD cross platform/board generic
encapsulated software architecture. This provides
the basic definitions and protocols for the follow-up
AMD open board project.
Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Cc: Igniculus Fu <igniculus.fu@amd.com>
Cc: Ken Yao <ken.yao@amd.com>
Cc: Eric Xing <eric.xing@amd.com>
Cc: Duke Zhai <Duke.Zhai@amd.com>
Signed-off-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Eric Xing <Eric.Xing@amd.com>
Reviewed-by: Ken Yao <Ken.Yao@amd.com>
Reviewed-by: Duke Zhai <duke.zhai@amd.com>
Reviewed-by: Paul Grimes < paul.grimes@amd.com>
Reviewed-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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