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43 hoursAmdMinBoardPkg/SetCacheMtrrLib: Fix VGA/ROM3 cacheability and TOM underflowAbdul Lateef Attar1-0/+1
Change the legacy VGA range (0xA0000-0xC0000) from Uncacheable to WriteThrough. Guard the TOM1-derived WriteBack MTRR range against TOM1 <= 1MB instead of unconditionally subtracting, avoiding a UINT64 underflow into a huge bogus range. Explicitly mark the ROM3 SPI/flash MMIO window (read from the FCH PMIOA base-address registers) as Uncacheable in SetCacheMtrrAfterEndOfPei(), which was previously left with whatever attribute the default MTRR left it in. Add the missing FCH_PMIOA_REG64 (AcpiPmTmrBlk) register offset to AgesaModulePkg's FchRegistersCommon.h - this package's copy is a hand-curated subset of AGESA's full register header and only had FCH_PMIOA_REG60 defined, so SetCacheMtrrAfterEndOfPei()'s new ROM3 base-address read failed to build. Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
43 hoursAmdPlatformPkg: Fix IA32 build, enable stuart CI build, clean up DSC/DSC.incAbdul Lateef Attar1-1/+1
Fix the IA32 build (stale BaseStackCheckLib mapping removed by upstream edk2, plus two typo'd library class names and one mismatched LIBRARY_CLASS), then enable the stuart CI pipeline for AmdPlatformPkg: - Add AmdPlatformPkg.ci.yaml. - Platform/AMD/CISettings.py: add edk2-platforms/Platform to GetPackagesPath() so MinPlatformPkg.dec resolves. - Fix every real issue the CI plugins found once running: formatting, #pragma once guards, missing SPDX headers, a stale INF abstract, missing/incorrect doxygen comments, a SpellCheck gap. Documented the remaining EccCheck false positives in the ci.yaml instead of leaving unexplained gaps. Clean up AmdPlatformPkg.dsc/.dsc.inc: - Move AmdPlatformPkg's own Components/LibraryClasses entries into .dsc.inc (the file board DSCs are meant to include), fixing two duplicate-listing bugs this exposed (PlatformHobPei.inf, EspiNorFlashSmm.inf each building twice). - Remove entries with no consumer anywhere this package builds, verified via both static grep and the real linked library closure in a full IA32+X64 build report. Confirmed board-level DSCs don't even consume these files, so this can't affect them. - Fix two latent bugs: an unconditional SerialPortLib line was always overriding the SIMNOW_PORT80_DEBUG conditional, and SpiHcPlatformLib had no ROM_ARMOR_ENABLED==FALSE fallback (silently used the Null stub instead of the real implementation). - Group [LibraryClasses.xxxx] by source repo and sort alphabetically; sort [Components.xxxx] alphabetically; move DXE/SMM-phase-only components out of arch-common sections into X64-specific ones. Verified full stuart_ci_build matrix (all 15 applicable checks pass) and ~/Scripts/build_tianocore.sh -p AmdPlatformPkg -b NOOPT -a IA32/X64 at every step. Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
43 hoursAmdPlatformPkg: Update the SPI flash stackAbdul Lateef Attar9-19/+200
Drop the deprecated SPI drivers, put BoardSpiConfig and EspiNorFlash, and add the SpiFvb variable and RDE response drivers. Rework SpiHcPlatformLib so the DXE and SMM instances share one hardware path, and drop the null instance. Which are now part of edk2 repo. Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
43 hoursAmdPlatformPkg: Add SpiHcRomArmorPlatformLibAbdul Lateef Attar4-0/+59
Build the ROM Armor SPI host-controller library for DXE and SMM. Platforms select it by setting ROM_ARMOR_ENABLED to TRUE, which maps SpiHcPlatformLib to these instances. The default remains FALSE, so the existing null SpiHcPlatformLib mapping is unchanged. Supporting changes: - Add PcdRomArmorWhitelistEnable to AgesaCommonModulePkg. - Map a null AmdEmulationAutoDetectLib for DXE and DXE_SMM. - Drop the local mFchDevicePath definition. AmdSpiDevicePaths.h already provides that object, and a second definition failed the build. Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
9 daysAmdPlatformPkg: Add DynamicTables — ConfigurationManagerDxe and ACPI libsAbdul Lateef Attar1-0/+3
ConfigurationManagerDxe (DXE_DRIVER): Implements EDKII_CONFIGURATION_MANAGER_PROTOCOL. Populates a static repository (EDKII_PLATFORM_REPOSITORY_INFO) with CM objects for: FACS, FADT, HPET, WSMT, SPMI, MCFG, MADT. Updates MADT from EFI_MP_SERVICES_PROTOCOL, MCFG from PciSegmentInfoLib, and HPET from hardware detection. Calls UpdatePlatformCmInfo() for SoC-specific data. NULL DXE libraries (linked into ConfigurationManagerDxe via DSC override): AcpiDsdtLib — installs pre-compiled Dsdt.asl as the platform DSDT AcpiSsdtCpuTopologyLib — generates CPU topology SSDT from MP-Services data AcpiSsdtEspiUartLib — conditionally installs eSPI UART SSDT AcpiSsdtPciLib — generates PCIe root bridge, USB, and system device SSDTs AcpiSsdtSerialLib — generates FCH UART SSDT (MMIO + legacy I/O paths) SampleCmPlatOverrideLib — demonstrates CM table override pattern for IBVs Required fixups: - Add 15 new PCDs to AmdPlatformPkg.dec [PcdsFixedAtBuild]: PcdAcpiSsdtSerialSkipOnSimNow, 9 x PcdAmdAcpi*OemTableId, PcdAmdNumaCcdOrder, 4 x PcdLegacyUartIrq0x*. - Add PcdUsePlatformAcpi and PcdAmdIdsUartBaudRate to AgesaPkg.dec. - Add PcdAmdSimNowEn to AmdCpmPkg.dec. - Add FCH_AL2AHBx20_LEGACY_UART_IO_ENABLE to FchRegistersCommon.h. - Add AmdConfigurationManager.h to AmdPlatformPkg/Include/. - Extend AmdPlatformSocLib.h/DxePlatformSocLibNull.c with the LinkHotplug/EcrcSupport fields and GetPcieEcrcSupport()/ UpdatePlatformCmInfo() hooks actually consumed by this module. - Map LocalApicLib and PciSegmentInfoLib for DXE_DRIVER in the DSC, and wire all 7 modules into AmdPlatformPkg.dsc/dsc.inc [Components.X64]. - Add missing SPDX-License-Identifier tags to 4 vendor .asl/.asi files. Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
14 daysAmdPlatformPkg: Add PciHotPlugInit DXE driverAbdul Lateef Attar1-0/+1
The PciHotPlugInit DXE driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL and provides resource padding information (bus, I/O, memory, prefetchable memory) for PCIe hot-plug slots. Padding amounts are configurable per-platform via PCDs. Supporting changes: - AmdPlatformPkg.dec: declare four FixedAtBuild PCDs (PcdPciHotPlugResourcePadIo/PMem/Mem/Bus) with default padding values - AgesaCommonModulePkg.dec: declare PcdValLoopbackMode (Dynamic UINT32) consumed by the driver to disable padding in loopback-mode test setups - AmdPlatformPkg.dsc.inc: add module to [Components.X64] Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
14 daysAmdPlatformPkg: Add PspPreTcgEventLogPei PEIMAbdul Lateef Attar1-0/+1
The PspPreTcgEventLogPei module retrieves PSP early-boot dTPM measurements via AmdPspDtpmPpi and deposits them as gTcgEventEntryHobGuid (TCG 1.2) and gTcgEvent2EntryHobGuid (TCG 2.0) HOBs. Tcg2Dxe replays these HOBs automatically in its SetupEventLog() phase, making the PSP-measured events visible in the TCG event log without any changes to Tcg2Dxe. Supporting changes: - AgesaModulePspPkg.dec: declare gAmdPspDtpmPpiGuid in [Ppis] - AgesaPkg/Include/Ppi/AmdPspDtpmPpi.h: add missing PPI header - AmdPlatformPkg.dsc: add PeimEntryPoint and Tpm2DeviceLib mappings under [LibraryClasses.common.PEIM] required by the new PEIM - AmdPlatformPkg.dsc.inc: add module to [Components.IA32] Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
14 daysAmdPlatformPkg: Add AmdPostCodeLibNull for AGESA post code interfaceAbdul Lateef Attar3-0/+48
AmdPostCodeLibNull is a no-op AmdPostCodeLib instance so AGESA modules that call LibAmdPostCode can link when a real post-code backend is not present. ACCESS_WIDTH is defined in AMD.h, AmdPostCodeLib.h declares LibAmdPostCode, and AmdPlatformPkg.dsc maps AmdPostCodeLib to the NULL instance. Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
2025-09-05AMD EDKII Platform Code v1.0.0.7 for 5th Generation EPYC ProcessorsPaul Grimes1-1/+1
Update of AMD EDKII Platform Code for 5th Generation EPYC Processors (formerly Turin). This sample platform code was tested to work with the Turin 1.0.0.7 AGESA PI package, which is available from AMD under license and NDA. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2025-04-23AMD EDKII Platform Code for 5th Generation EPYC ProcessorsPaul Grimes7-173/+0
Update of AMD EDKII Platform Code for 5th Generation EPYC Processors (formerly Turin). This sample platform code was tested to work with the Turin 1.0.0.5 AGESA PI package, which is available from AMD under license and NDA. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2025-03-14Initial commit of AMD EDKII Platform Code for 5th Generation EPYC ProcessorsPaul Grimes112-336/+1734
Initial commit of AMD EDKII Platform Code for 5th Generation EPYC Processors (formerly Turin). This sample platform code was tested to work with the Turin 1.0.0.4 AGESA PI package, which is available from AMD under license and NDA. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2024-05-24Platform/AMD: Initial commit of cross platform/board interfacesAbner Chang98-0/+13842
BZ#: 4777 Initial commit of AMD cross platform/board generic encapsulated software architecture. This provides the basic definitions and protocols for the follow-up AMD open board project. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Igniculus Fu <igniculus.fu@amd.com> Cc: Ken Yao <ken.yao@amd.com> Cc: Eric Xing <eric.xing@amd.com> Cc: Duke Zhai <Duke.Zhai@amd.com> Signed-off-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Eric Xing <Eric.Xing@amd.com> Reviewed-by: Ken Yao <Ken.Yao@amd.com> Reviewed-by: Duke Zhai <duke.zhai@amd.com> Reviewed-by: Paul Grimes < paul.grimes@amd.com> Reviewed-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 04:18:19 +0300