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This is a preparatory patch to support runtime capsule updates,
where image authentication is performed by the update agent
running in StMM. The authentication process requires large buffer
allocations to authenticate the firmware image.
For this, TF-A updates the ARM_TZC_DRAM1_SIZE from 16MB to 64MB
in case of SPMC_AT_EL3 is used with PSA_FWU_SUPPORT.
As ARM_TZC_DRAM1_SIZE is increased, some of memory region definitions in
*.dsc files should be changed since the image base of StandaloneMm is
changed acoordingly [0].
Therefore, update those regions to work properly.
Link: [0] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/53044/6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Fix build for unused variable warning when build FwsGptSystemFipLib
with clang.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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When gen_gpt_flash.sh generates GPT partition image, it uses
sgdisk command and -u argument format should be like:
-u $partition_number:$unique_partition_uuid.
However, create_gpt_partition() doesn't pass the partition_number in -u
option as the result, it generates the null-uuid in some partition:
sfdisk --dump flash_gpt.img
label: gpt
label-id: 59FA9956-0969-4EDD-9D11-84C5AE24E334
device: flash_gpt.img
unit: sectors
first-lba: 34
last-lba: 131038
sector-size: 512
flash_gpt.img1 : start= 34, size= 40960, type=49757D90-6C22-11EE-A556-1757EBA0420C, uuid=00000000-0000-0000-0000-000000000000, name="FIP_A"
flash_gpt.img2 : start= 40994, size= 40960, type=49757D90-6C22-11EE-A556-1757EBA0420C, uuid=55C65272-AB79-4EDE-9036-D96C971DBF98, name="FIP_B"
flash_gpt.img3 : start= 81954, size= 2048, type=8A7A84A0-8387-40F6-AB41-A8B9A5A60D23, uuid=00000000-0000-0000-0000-000000000000, name="FWU-Metadata"
flash_gpt.img4 : start= 84002, size= 2048, type=8A7A84A0-8387-40F6-AB41-A8B9A5A60D23, uuid=F9598889-EC4F-424D-B6ED-78C5BC12C4DF, name="Bkup-FWU-Metadata"
Fix this problem.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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As edk2 pr [0] add support generation of SMBIOS type 43 TPM table,
generate SMBIOS 43 table in Juno platform.
Link: [0] https://github.com/tianocore/edk2/pull/13175
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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As edk2 pr[0] updates CM_ARCH_COMMON_TPM_DEVICE_INFO structure to
generate SMBIOS type 43, update TPM device information with proper
information.
Link: [0] https://github.com/tianocore/edk2/pull/13175
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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As edk2 pr [0] add support generation of SMBIOS type 43 TPM table,
generate SMBIOS 43 table in VExpress platform.
Link: [0] https://github.com/tianocore/edk2/pull/13175
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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As edk2 pr[0] updates CM_ARCH_COMMON_TPM_DEVICE_INFO structure to
generate SMBIOS type 43, update TPM device information with proper
information.
Link: [0] https://github.com/tianocore/edk2/pull/13175
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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VariableMmDependencyLib is for DXE_DRIVER not for StandaloneMm.
Therefore, remove the Library in StandaloneMm build.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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The fTPM functionality is moved from FtpmSmm to TpmCrbFfaFtpmLib
which is instance of TpmCrbFfaDeviceLib.
Therefore, rename FtpmSmm to TpmCrbOverFfaSmm and remove fTPM relevant
features so that TpmCrbOverFfaSmm could be used with dTPM in the future
by implementing TpmCrbFfaDeviceLib.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add TpmCrbFfaFtpmLib which the implemantion of TpmCrbFfaDeviceLib with
fTPM (TpmLib) so that TpmCrbOverFfa StandaloneMm driver can handle
TPM request via fTPM.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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TpmCrbFfaDeviceLib defines the interfaces for accessing a TPM through
the CRB over FF-Ainterface and for handling TPM requests received
by the TPM CRB over FF-A driver.
The TPM CRB over FF-A Standalone MM driver uses this library to access
the backend TPM device and process requests received over FF-A.
The library provides an abstraction that can support various TPM
implementations, including fTPMs and dTPMs.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Since edk2 commit 2c2f74a58147 ("SecurityPkg: Break out the user prompt from Tcg2 PPI"),
Tcg2PhysicalPresenceLib requires Tcg2PhysicalPresencePromptLib.
To build properly, add Tcg2PhysicalPresencePromptLib.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Since edk2 commit 2c2f74a58147 ("SecurityPkg: Break out the user prompt from Tcg2 PPI"),
Tcg2PhysicalPresenceLib requires Tcg2PhysicalPresencePromptLib.
To build properly, add Tcg2PhysicalPresencePromptLib.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add AmdMinBoardPkg.ci.yaml, wiring up the Stuart CI plugins for this
package (LicenseCheck, EccCheck with an ExceptionList for library
classes ECC can't resolve without the full PACKAGES_PATH,
DscCompleteCheck, HostUnitTestDscCompleteCheck, GuidCheck, SpellCheck,
CodeQlAnalyze, etc.), and AmdMinBoardPkg.inc.dsc, a shared DSC include
with this package's phase-scoped library-class mappings
(ReportFvLib/PlatformSecLib/SpcrDeviceLib, BoardInitLib/SetCacheMtrrLib
for PEIM, BoardBdsHookLib for DXE_DRIVER) for platforms that include
this package elsewhere.
Add StackCheckLib|StackCheckLibNull to [LibraryClasses.common] (now
required by newer BaseTools), move [PcdsDynamicDefault] next to
[Packages], and drop the [BuildOptions] block (DISABLE_NEW_DEPRECATED_
INTERFACES/USE_EDKII_HEADER_FILE/MDEPKG_NDEBUG flags), which is no
longer needed with the rest of this update.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Add SpcrFeaturePkg/SpcrFeaturePkg.dec to the [Packages] section, needed
for this library's SPCR device support on newer platforms.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Change the legacy VGA range (0xA0000-0xC0000) from Uncacheable to
WriteThrough. Guard the TOM1-derived WriteBack MTRR range against
TOM1 <= 1MB instead of unconditionally subtracting, avoiding a UINT64
underflow into a huge bogus range. Explicitly mark the ROM3 SPI/flash
MMIO window (read from the FCH PMIOA base-address registers) as
Uncacheable in SetCacheMtrrAfterEndOfPei(), which was previously left
with whatever attribute the default MTRR left it in.
Add the missing FCH_PMIOA_REG64 (AcpiPmTmrBlk) register offset to
AgesaModulePkg's FchRegistersCommon.h - this package's copy is a
hand-curated subset of AGESA's full register header and only had
FCH_PMIOA_REG60 defined, so SetCacheMtrrAfterEndOfPei()'s new ROM3
base-address read failed to build.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Vendor the AGESA cache-as-RAM/stack-setup NASM includes (NasmBase.inc,
EarlyCpuSupportNasm.inc, CpStackNasm.inc, CpStackHooksNasm.inc,
AmdUefiStackNasm.inc) locally instead of depending on AGESA.h, and drop
the AGESA.h include and AgesaPkg/AgesaModulePkg/UefiCpuPkg package
dependencies from PlatformSecLib.c/.inf.
Remove the early MMIO config-space base MSR (0xC001_0058) setup from
Flat32.nasm's ProtectedModeEntryPoint (redundant with AGESA's own
setup), and move the BoardAfterTempRamInitWrapper() board-hook call to
after the BIST value is captured, so TSC/BIST data is saved before
board hooks run. Enable the local APIC in SEC phase
(AsmMsrOr64(MSR_IA32_APIC_BASE, BIT11)) ahead of PEI.
Rename gTopOfTemporaryRamPpiGuid to gAmdTopOfTemporaryRamPpiGuid
(avoiding a name collision with the identically-named PPI in other
packages) and fold its declaration into this package's existing [Ppis]
section, deleting the now-redundant Ppi/TopOfTemporaryRam.h header -
AmdWrapperPlatformSecLib.c/PlatformSecLib.inf publish it directly, and
SecGetPerformance.c is rewritten to read BIST/TSC data via
AsmSecPlatformGetTemporaryStackBase() instead of locating the PPI.
Add overflow checks around BIST-record size/offset arithmetic in
SecPlatformInformation() and the temp-RAM range computed in
BoardAfterTempRamInitWrapper(), replacing raw pointer math that could
wrap. Rename the fixed MTRR MSR index defines to consistent upper-case
local definitions (AMD_AP_MTRR_FIX64K_00000, etc.) instead of the
AGESA-supplied lower-case names.
Map PlatformSecLib under the new [LibraryClasses.common.SEC] DSC
section instead of the generic [LibraryClasses]/
[Components.IA32, Components.X64] sections.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Drop the FSP-T FV install path (dead code - FSP isn't used) and the
above-4GB firmware-volume handling: FvUefiBoot/FvOsBoot/FvAdvanced/
FvAdvancedSecurity are now always installed via
PeiServicesInstallFvInfo2Ppi() at their (32-bit) PcdFlashFv*Base
addresses, instead of conditionally building EFI_HOB_TYPE_FV/FV3 HOBs
when the corresponding 64-bit PcdAmdFlashFv*Base PCD was >= 4GB.
Replace the removed PcdAmdFlashFvAdvancedBase/OsBootBase/UefiBootBase/
AdvancedSecurityBase (UINT64) PCDs with a 32-bit
PcdFlashFvAdvancedSecurityBase declared in this package, and report the
FvAdvanced-to-FvPreMemory flash range as a system-memory resource
(cacheable) instead of the previous flat MMIO resource HOB covering
just PcdFlashAreaBase/Size, reflecting that these FVs are consumed from
DRAM-shadowed flash rather than the ROM3 MMIO window.
Replace ASSERT_EFI_ERROR() with an explicit status check and early
return when PeiServicesGetBootMode() fails.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Add AMD_MEMORY_ATTRIBUTE_GPU_SP, _HBM, _PERSISTENT_MEMORY and
_RESERVED_X4_PUSH_WRITE memory range attributes so newer AMD SoC
memory maps (HBM/SPM/GPU address ranges) can be reported correctly.
Rework EndofAmdMemoryInfoHobPpiGuidCallBack(): introduce a data-driven
mBelow4GbCarveouts[] table (IOAPIC/HPET/TPM2, sourced from FixedPcd)
plus SortCarveoutsByBase(), so below-4GB MMIO gaps around these fixed
resources are reported to the GCD individually (with Memory Allocation
HOBs where required) instead of as one opaque MMIO resource HOB; new
carve-outs only require a table entry. Guard the SMRAM-carve-from-
available-RAM path against undersized below-4GB ranges and TOM1
sitting exactly at 4GB.
Change PcdAmdSmramAreaSize from UINT64 to UINT32 (matching its actual
32-bit usage) and move it to [FixedPcd] in the INF alongside the new
HPET/IOAPIC/TPM base-address FixedPcds the carve-out table consumes.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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reservation
Remove the FADT/MADT/DSDT/SSDT ACPI-table runtime patching path -
BoardInitReadyToBoot() no longer calls FadtAcpiTablePatch(),
MadtAcpiTablePatch(), or AcpiTableAmlUpdate(). Delete the now-unused
MadtAcpiTablePatch.c and the UpdateReinstallAcpiTable() helper, and
drop the BoardAcpiTableLib|BoardAcpiTableLibNull mapping this path
depended on.
Replace ReservePcieExtendedConfigSpace() with ReserveFadtIoResources(),
which reports the FADT-defined PM1a/PM1 control/PM timer/GPE0/SMI
command port ranges to the GCD via a new generic ReportIoRangeToGcd()
helper, instead of reserving PCIe extended config space MMIO.
Drop the now-unused LocalApicLib/PcieConfigLib/PlatformSocLib/SortLib
library dependencies and the AmdPlatformPkg/MdeModulePkg/UefiCpuPkg
package references that supported the removed code paths, replacing
them with AgesaPkg/PcAtChipsetPkg and the FCH ACPI PM/GPE0/SMI PCDs
consumed by ReserveFadtIoResources().
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Extract HandleIpmiBootOverride() out of BoardBdsHookLib.c into a new
BoardIpmiBootOverride.c, and switch its priority-override lookup to
consume gAmdBoardBdsBootOptionPriorityProtocolGuid from AmdPlatformPkg's
shared protocol header instead of a copy of the GUID/struct declared
locally in this package's DEC/AmdBoardBdsHookLib.h.
Fix boot order: BootOptionPriority()/HddBootOptionPriority() had the
PXE and HDD priority values swapped, causing HDD to sort behind PXE;
corrected the priorities so the boot order matches the documented
table.
Replace ASSERT_EFI_ERROR()/silent failures with explicit status checks
and DEBUG_ERROR logging across BDS hook callbacks, boot-menu
registration, and shell text-mode switching. Add const-correctness,
signed/unsigned and pointer-arithmetic fixes (BootOptionType()/
BootOptionPriority() return MAX_UINT8/INTN instead of relying on
(UINT8)-1/UINTN wraparound; OptionIndex handled as a signed INTN before
the "not found" check) and overflow guards in GetGraphicsController()
(PciHandlesSize/NumDevices bounds checks) to close Coverity/CERT-C
findings. Clamp PcdPlatformMemoryCheckLevel to MAXLEVEL before calling
MemoryTest() to avoid an out-of-range EXTENDMEM_COVERAGE_LEVEL cast.
Publish BoardBdsHookLib as a [LibraryClasses] entry in the DEC (with
its header moved to Include/Library/AmdBoardBdsHookLib.h) and map/
register it under [LibraryClasses.common.DXE_DRIVER]/[Components.X64]
in the DSC.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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This module is moved to the AmdPlatformPkg package.
Hence removing it from this package.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Fix the IA32 build (stale BaseStackCheckLib mapping removed by upstream
edk2, plus two typo'd library class names and one mismatched
LIBRARY_CLASS), then enable the stuart CI pipeline for AmdPlatformPkg:
- Add AmdPlatformPkg.ci.yaml.
- Platform/AMD/CISettings.py: add edk2-platforms/Platform to
GetPackagesPath() so MinPlatformPkg.dec resolves.
- Fix every real issue the CI plugins found once running: formatting,
#pragma once guards, missing SPDX headers, a stale INF abstract,
missing/incorrect doxygen comments, a SpellCheck gap. Documented the
remaining EccCheck false positives in the ci.yaml instead of leaving
unexplained gaps.
Clean up AmdPlatformPkg.dsc/.dsc.inc:
- Move AmdPlatformPkg's own Components/LibraryClasses entries into
.dsc.inc (the file board DSCs are meant to include), fixing two
duplicate-listing bugs this exposed (PlatformHobPei.inf,
EspiNorFlashSmm.inf each building twice).
- Remove entries with no consumer anywhere this package builds, verified
via both static grep and the real linked library closure in a full
IA32+X64 build report. Confirmed board-level DSCs don't even consume
these files, so this can't affect them.
- Fix two latent bugs: an unconditional SerialPortLib line was always
overriding the SIMNOW_PORT80_DEBUG conditional, and SpiHcPlatformLib had
no ROM_ARMOR_ENABLED==FALSE fallback (silently used the Null stub
instead of the real implementation).
- Group [LibraryClasses.xxxx] by source repo and sort alphabetically;
sort [Components.xxxx] alphabetically; move DXE/SMM-phase-only
components out of arch-common sections into X64-specific ones.
Verified full stuart_ci_build matrix (all 15 applicable checks pass) and
~/Scripts/build_tianocore.sh -p AmdPlatformPkg -b NOOPT -a IA32/X64 at
every step.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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DefaultLomDevicePath.c is removed; LOM device-path lookup
stays in AmdBdsBootConfigLib.
The driver now adds these records, in type order:
- Type 0 BIOS vendor, using GetBoardBiosInfo and the type 0 PCDs.
- Type 1 system, type 2 baseboard, and type 3 chassis manufacturer.
- Type 21 built-in pointing device.
- Type 26 voltage probe.
- Type 32 boot information.
- Type 39 system power supply.
- Type 42 management controller host interface.
Type 9 slot records set SlotInformation to 6 when SlotType is PCIe Gen6 or
later, and 0 otherwise, as required by SMBIOS 3.9. Types 8, 11, 12, 13, 38,
and 41 stay, with the platform string and size checks.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Enroll KEK and db with signature owner 77FA9ABD-0359-4D32-BD60-28F4E78F784B
instead of gEfiGlobalVariableGuid. dbx stays under the global variable GUID.
- Name PKDefault, KEKDefault, dbDefault, and dbxDefault with the local
variable-name strings.
- Accept an EFI_VARIABLE_AUTHENTICATION_2 blob that is larger than the header.
The previous check rejected every signed Microsoft dbx update and stored the
whole blob as one X509 entry. Copy the header into an aligned buffer before
reading the certificate length.
- Treat EFI_UNSUPPORTED from an init helper as success. That status means the
default variable already exists and its value is preserved.
- Drop SecureBootVariableLib and SecureBootVariableProvisionLib. This driver
writes the default variables directly.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Read the SPI address-window register through FCH_SPI_MMIO_REG5C_ADDR32_CTRL3.
The header aliases that name to the
existing mixed-case register, so the MMIO offset is unchanged.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Use #pragma once in Logo.h instead of an include guard.
- Drop the unused GraphicsOutput and HiiPackageList includes, and the
AMD_EDKII_OVERRIDE marker, from Logo.c.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Stop string scans and appends when the length would wrap MAX_UINTN, and
reject a hex digit that would overflow a byte.
- Restore the caller's '&' when an append fails after it was temporarily
replaced with a NUL.
- Treat a missing OFFSET, WIDTH, or VALUE element as EFI_INVALID_PARAMETER
instead of continuing from a NULL pointer.
- Report BlockSize as zero when no block bytes were consumed.
- Rename the element-header enum to HII_ELEMENT_HDR and declare HiiStrnCmp
and AmdConfigRoutingEntry in the header.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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The port 80 serial library does not call BaseLib. Removing the include
keeps the translation unit limited to IoLib and SerialPortLib.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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The null PlatformSocLib was missing the SoC hooks used by SMBIOS and PCIe
platform code, so a consumer of this library failed to link. Each new
function returns EFI_UNSUPPORTED, which is the null-library contract: the
platform does not supply the data and the caller skips that record.
Added stubs:
- GetPcieEcrcSupport, looked up by PCI segment and bus.
- GetSystemPowerSupplyInfo for SMBIOS type 39.
- GetPortingDeviceInfo for SMBIOS type 21.
- GetVoltageProbeInfo.
- GetBoardBiosInfo for SMBIOS type 0.
The INF now depends on AmdPlatformPkg.dec so those platform structure types
resolve. GetIoApicInfo and GetPcieInfo comments now list the EFI_STATUS
values the real library can return.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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On PCI enumeration complete, the library reads the IPMI boot
initiator mailbox. When the mailbox carries the AMD IANA id and a boot
override, it configures DHCP and prefers the PXE NIC on that subnet.
Otherwise it installs the LOM as the default PXE device through
gAmdBoardBdsBootOptionPriorityProtocolGuid. ConfigureDhcp.c is new in this
tree; the previous copy depended on BoardBdsHookLib and IpmiCommandLib.
Supporting package changes:
- Add Include/AmdIanaId.h and Include/Protocol/AmdBootOptionPriorityProtocol.h.
- Declare gAmdBoardBdsBootOptionPriorityProtocolGuid in AmdPlatformPkg.dec.
The GUID matches the existing AmdMinBoardPkg declaration.
- Add fixed PCD PcdAmdGetIpInfoRetryCount (100, token 0x00040004).
- Map NetLib and NbioCommonDxeLib for DXE_DRIVER.
- Build AmdBdsBootConfigLib.inf from [Components.X64].
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Drop the unused PiSmm.h and BaseMemoryLib includes.
- Annotate the LIST_ENTRY container-of walks in PlatformHookBeforeSmmDispatch
and PlatformHookAfterSmmDispatch with the Coverity EXP39-C.
Deriving the hook record from an embedded LIST_ENTRY is the
normal EDK II list pattern.
- Remove gAmdSpiHcStateProtocolGuid from the INF. SPI host-controller state
is owned by SmmCoreAmdSpiHcHookLib, and this library does not consume that
protocol.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Drop the unused BaseLib include from SmmCoreAmdSpiHcHookLib.c.
- Use #pragma once in the header instead of an include guard.
- List SmmCoreAmdSpiHcHookLib.h in the INF [Sources] section.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Drop the deprecated SPI drivers, put BoardSpiConfig and
EspiNorFlash, and add the SpiFvb variable
and RDE response drivers. Rework SpiHcPlatformLib so the DXE and SMM
instances share one hardware path, and drop the null instance.
Which are now part of edk2 repo.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Build the ROM Armor SPI host-controller library for DXE and SMM.
Platforms select it by setting ROM_ARMOR_ENABLED to TRUE, which maps
SpiHcPlatformLib to these instances. The default remains FALSE, so the
existing null SpiHcPlatformLib mapping is unchanged.
Supporting changes:
- Add PcdRomArmorWhitelistEnable to AgesaCommonModulePkg.
- Map a null AmdEmulationAutoDetectLib for DXE and DXE_SMM.
- Drop the local mFchDevicePath definition. AmdSpiDevicePaths.h already
provides that object, and a second definition failed the build.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Adds TPM2 DXE driver so SystemGuard NV index setup and
platform hierarchy configuration are available in the tianocore package build.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Use a common DSC include to honor EDK2_OUT_DIR across all ARM
platforms. Keep the existing default paths, including the Juno and
VExpress Standalone MM paths, when no override is supplied.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
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The last three tables are specific to FVP RevC, while the TPM2 table is
also supported on the FVP AEM platform.
Therefore, move the TPM2 table to the appropriate location.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Add documentation for enabling GICv5 support with FVP_RevC model.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Update PCI interrupt value from SPI to IWB and _PRT table entry.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Currently, platform coordinated LPI isn't supported with gic-v5.
Therefore, disable it.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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This patch add support for GICv5 in FVP_RevC model.
For this:
- add IRS, ITSv5, IWB information.
- add DSDT for GicV5.
- update IORT information.
- update Platform repository when GICv5 is supported.
Link: https://developer.arm.com/documentation/110379/1131/Base-Platform/FVP-Base-RevC-2xAEMvA-GICv5-platform-interrupt-assignments?lang=en [0]
Signed-off-by: Sarah Walker <Sarah.Walker@arm.com>
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Generate SRAT table.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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According to FVP Base platform interrupt assignments [0],
PCIE interrupt start from 200 and SPI offset 168.
In the CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO, interrupt information
should be set with INTR_ID not SPI offset.
Change PCIE interrupt-id according to spec.
Link: [0] https://support.arm.com/documentation/110379/1132/Base-Platform/Base-Platform-interrupt-assignments
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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Some of file inside of Platform/ARM mixed with LF/CRLF and this makes
a great trouble to read/review code.
Change all of file format to CRLF.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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This DXE_DRIVER
produces EFI_SYS_TOPOLOGY_PROTOCOL, which walks enumerated PCI devices
(via gEfiPciIoProtocolGuid), NVMe/AHCI/IDE storage (via
NvmExpressPassThru/DiskInfo/BlockIo), and SMBIOS records to build a
serializable system topology report (PCIe endpoints, storage devices,
memory, BIOS version) for consumers such as Redfish.
Required fixups:
- Add Include/Protocol/SysTopologyProtocol.h (defines
EFI_SYS_TOPOLOGY_PROTOCOL and the report/entry structures) --
missing SPDX-License-Identifier tag added.
- Add gEfiSysTopologyProtocolGuid to AmdPlatformPkg.dec [Protocols].
- Wire into AmdPlatformPkg.dsc.inc [Components.X64].
All other dependencies (NvmExpressPassthru.h, DiskInfo.h, BlockIo.h,
PciIo.h, Smbios.h, IndustryStandard/Nvme.h, Atapi.h, SmBios.h, and
their GUIDs/protocols) already exist in core edk2 MdePkg/MdeModulePkg.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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This PEIM notifies on
EDKII_PEI_MP_SERVICES2_PPI to call SmmRelocationInit() (relocating each
processor's SMBASE), then, outside S3 resume and when Modern Standby is
not enabled (detected via presence of gAmdCpmTablePpiGuid), allocates
reserved memory for S3 and records its base/size into the ACPI S3
range structure found via the gEfiSmmSmramMemoryGuid HOB.
Required fixups:
- Add PcdS3ExtraMemSize to AmdPlatformPkg.dec [PcdsFixedAtBuild].
- Add AcpiS3MemReserve.h to AmdPlatformPkg/Include/.
- Add Ppi/AmdCpmTablePpi/AmdCpmTablePpi.h to AmdCpmPkg/Include/ -- no
production header for this PPI exists in Venice or tianocore, only a
host-test mock ({UINT32 Revision;}). Per user direction, promoted that
struct to the real header: this module only checks LocatePpi's return
pointer for non-NULL, never dereferences fields, so the mock's shape
is functionally sufficient.
- Map SmmRelocationLib->AmdSmmRelocationLib, plus its own transitive
PEIM dependencies (CpuExceptionHandlerLib->SecPeiCpuExceptionHandlerLib,
LocalApicLib->BaseXApicX2ApicLib, CcExitLib->CcExitLibNull) under
AmdPlatformPkg.dsc [LibraryClasses.common.PEIM].
- Wire into AmdPlatformPkg.dsc.inc [Components.IA32].
- Drop an unrelated duplicated block of 6 [Components.X64] lines
(AmdSpiHcSmm.inf, AmdSpiHcDxe.inf, EspiNorFlashSmm.inf, AcpiCommon.inf,
BoardSpiConfigDxe.inf, BoardSpiConfigSmm.inf) that had been
accidentally pasted twice in AmdPlatformPkg.dsc.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Add NvStoreRestoreDefaultSmm driver. This
DXE_SMM_DRIVER registers a notify on gEfiSpiSmmNorFlashProtocolGuid
and, when the active variable store PCD points at the default image,
compares the primary and default NV variable regions on SPI flash and
restores the primary region (plus its FTW header) from the default
image if they differ, then switches PcdFlashNvStorageVariableBase back
to the primary region.
Required fixups:
- Add PcdFlashNvStorageVariablePrimaryBase, PcdFlashNvStorageVariable-
DefaultSize, PcdFlashNvStorageBlockSize, and PcdFlashAreaBaseAddress
to AmdPlatformPkg.dec [PcdsFixedAtBuild] (grouped with the existing
NV-store PCDs used by RestoreDefaultPei); the token values are
renumbered from Venice's to avoid colliding with PCDs already
assigned in this DEC by earlier ports.
- FCH_SPI_MMIO_REG5C_ADDR32_CTRL3 -> FCH_SPI_MMIO_REG5C_Addr32_Ctrl3
(tianocore FchRegistersCommon.h uses mixed-case register names).
- Map MmServicesTableLib and PcdLib->DxePcdLib (needed for the
PcdSet32S call on the already-dynamic PcdFlashNvStorageVariableBase)
under AmdPlatformPkg.dsc [LibraryClasses.common.DXE_SMM_DRIVER] --
first DXE_SMM_DRIVER module ported on this branch.
- Wire into AmdPlatformPkg.dsc.inc [Components.X64].
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Add PlatformHobPei library. This PEIM produces a
gMmCommBufferHobGuid HOB (MM_COMM_BUFFER) sized from
PcdMmCommBufferPages, registered via a notify on EndOfPei, for use by
the MM communication buffer consumers later in boot.
No supporting-package changes were needed: the GUID, PCD, and PPI this
module depends on (gMmCommBufferHobGuid, PcdMmCommBufferPages,
gEfiEndOfPeiSignalPpiGuid) already exist in edk2 MdeModulePkg/MdePkg.
Wired into AmdPlatformPkg.dsc.inc [Components.IA32] and [Components.X64].
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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ConfigurationManagerDxe (DXE_DRIVER):
Implements EDKII_CONFIGURATION_MANAGER_PROTOCOL. Populates a static
repository (EDKII_PLATFORM_REPOSITORY_INFO) with CM objects for:
FACS, FADT, HPET, WSMT, SPMI, MCFG, MADT. Updates MADT from
EFI_MP_SERVICES_PROTOCOL, MCFG from PciSegmentInfoLib, and HPET from
hardware detection. Calls UpdatePlatformCmInfo() for SoC-specific data.
NULL DXE libraries (linked into ConfigurationManagerDxe via DSC override):
AcpiDsdtLib — installs pre-compiled Dsdt.asl as the platform DSDT
AcpiSsdtCpuTopologyLib — generates CPU topology SSDT from MP-Services data
AcpiSsdtEspiUartLib — conditionally installs eSPI UART SSDT
AcpiSsdtPciLib — generates PCIe root bridge, USB, and system device SSDTs
AcpiSsdtSerialLib — generates FCH UART SSDT (MMIO + legacy I/O paths)
SampleCmPlatOverrideLib — demonstrates CM table override pattern for IBVs
Required fixups:
- Add 15 new PCDs to AmdPlatformPkg.dec [PcdsFixedAtBuild]:
PcdAcpiSsdtSerialSkipOnSimNow, 9 x PcdAmdAcpi*OemTableId,
PcdAmdNumaCcdOrder, 4 x PcdLegacyUartIrq0x*.
- Add PcdUsePlatformAcpi and PcdAmdIdsUartBaudRate to AgesaPkg.dec.
- Add PcdAmdSimNowEn to AmdCpmPkg.dec.
- Add FCH_AL2AHBx20_LEGACY_UART_IO_ENABLE to FchRegistersCommon.h.
- Add AmdConfigurationManager.h to AmdPlatformPkg/Include/.
- Extend AmdPlatformSocLib.h/DxePlatformSocLibNull.c with the
LinkHotplug/EcrcSupport fields and GetPcieEcrcSupport()/
UpdatePlatformCmInfo() hooks actually consumed by this module.
- Map LocalApicLib and PciSegmentInfoLib for DXE_DRIVER in the DSC, and
wire all 7 modules into AmdPlatformPkg.dsc/dsc.inc [Components.X64].
- Add missing SPDX-License-Identifier tags to 4 vendor .asl/.asi files.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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