starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2024-08-27	clk: starfive: jh7110: Drop i2c core clock	Hal Feng	1	-21/+0
	Enable i2c apb clock is enough, the core clock is redundant. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29	clk: starfive: jh7110: Add full i2c clocks	Hal Feng	1	-18/+52
	Correct the parent of i2c clocks and add full i2c clocks. The code mainly is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-04-23	board: starfive: copyright: Standardize the copyright format	Yanhong Wang	1	-1/+1
	Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-02-22	clk: starfive: Add PCIe clocks for PCIe controller	Mason Huo	1	-0/+43
	Add the stg clocks for PCIe controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-17	i2c:desigware-snps: add i2c clock config	keith.zhao	1	-0/+18
	add clock config for i2c2 and i2c5 update the i2c driver clock config Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-01-05	clk:starfive: Add vout clock driver for StarFive JH7110	Yanhong Wang	1	-198/+433
	Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-10-18	clk: starfive: jh7110: Modify the parameters of clk_register()	Yan Hong Wang	1	-34/+11
	Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:jh7110: update apb_bus clk relationship	yanhong.wang	1	-26/+7
	The previous definition of apb_bus clock relationship is incorrect,so update it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:jh7110: pll0 dynamically gets the frequency	samin	1	-5/+35
	pll0 dynamically gets the frequency. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18	clk:riscv:starfive: update uart3-uart5 clks	yanhong.wang	1	-16/+24
	Update uart3-uart5 clks register info for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:starfive-jh7110: Update pll0/pll1/pll2 clk	yanhong.wang	1	-6/+4
	Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:starfive-jh7110: add JH7110_GMAC1_GTXC clk	yanhong.wang	1	-0/+4
	Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:starfive-jh7110: Update pll0/pll1/pll2 clk	yanhong.wang	1	-3/+7
	Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macros	yanhong.wang	1	-2/+2
	Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:starfive-jh7110: remove unused clk	yanhong.wang	1	-52/+4
	Remove unused clock in order to reduce code size. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18	clk:starfive-jh7110: Add clock driver for JH7110	yanhong.wang	3	-0/+706
	Add a clock driver for StarFive JH7110 Soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>