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path: root/drivers/clk
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2024-08-27clk: starfive: jh7110: Drop i2c core clockHal Feng1-21/+0
Enable i2c apb clock is enough, the core clock is redundant. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29clk: starfive: jh7110: Add full i2c clocksHal Feng1-18/+52
Correct the parent of i2c clocks and add full i2c clocks. The code mainly is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang1-1/+1
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-02-22clk: starfive: Add PCIe clocks for PCIe controllerMason Huo1-0/+43
Add the stg clocks for PCIe controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-17i2c:desigware-snps: add i2c clock configkeith.zhao1-0/+18
add clock config for i2c2 and i2c5 update the i2c driver clock config Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-198/+433
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk: starfive: jh7110: Modify the parameters of clk_register()Yan Hong Wang1-34/+11
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: update apb_bus clk relationshipyanhong.wang1-26/+7
The previous definition of apb_bus clock relationship is incorrect,so update it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: pll0 dynamically gets the frequencysamin1-5/+35
pll0 dynamically gets the frequency. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18clk:riscv:starfive: update uart3-uart5 clksyanhong.wang1-16/+24
Update uart3-uart5 clks register info for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-6/+4
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: add JH7110_GMAC1_GTXC clkyanhong.wang1-0/+4
Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-3/+7
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macrosyanhong.wang1-2/+2
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: remove unused clkyanhong.wang1-52/+4
Remove unused clock in order to reduce code size. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Add clock driver for JH7110yanhong.wang5-0/+708
Add a clock driver for StarFive JH7110 Soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-09-17clk: ti: k3: Update driver to account for divider flagsSuman Anna1-2/+2
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach1-2/+11
There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-08-25drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim3-0/+221
Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim3-1/+708
Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-22clk: clk_versaclock: Add support for versaclock driverAdam Ford3-0/+1110
The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-16clk: stm32mp1: add support of BSEC clockPatrick Delaunay1-0/+1
Add the support of the BSEC clock used by the STM32MP misc driver since the commit 622c956cada0 ("stm32mp: bsec: manage clock when present in device tree") even if this clock is not yet defined in kernel device tree stm32mp151.dtsi. This patch avoids issue for basic boot when this secure clock are not provided by secure world with SCMI. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-12rockchip: px30: Support configure SFCJon Lin1-0/+32
Make px30 SFC clock configurable Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-07-27clk: stm32mp1: add support of missing SPI clocksPatrick Delaunay1-0/+13
Add the missing SPI clock even if these instances are not available on STMicroelectronics boards: SPI2_K, SPI3_K, SPI4_K, SPI6_K. With this patch, the SPI2 / SPI3 / SPI4 / SPI6 instances can be used on customer design without the clock driver error: stm32mp1_clk_get_id: clk id 131 not found Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-26clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek1-0/+1
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini1-1/+22
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-16Merge branch '2021-07-15-assorted-fixes'Tom Rini1-1/+5
- Large number of Coverity reported issues addressed - m41t62 bugfix - Support more Android image compression formats - FIT + DTO bugfix
2021-07-16clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay1-0/+1
Add the support of SYSCFG clock used by syscon driver to prepare the clock management of STM32MP_SYSCON_SYSCFG. This clock is already defined in kernel device tree, stm32mp151.dtsi but not yet supported in the syscon driver: syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&rcc SYSCFG>; }; It is safe to support this clock in U-Boot driver with RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16clk: Detect failure to set defaultsSimon Glass1-1/+5
When the default clocks cannot be set, the clock is silently probed and the error is ignored. This is incorrect, since having the clocks at the correct speed may be important for operation of the system. Fix it by checking the return code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-14clk: uniphier: Add PCIe clock entryKunihiko Hayashi1-0/+3
Add clock control for PCIe controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-10clk: imx8mm: Add SPI clocksFrieder Schrempf1-1/+22
Add the clocks for the ECSPI controllers. This is ported from Linux v5.13-rc4. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-08clk: armada-37xx: Set DM_FLAG_PRE_RELOCMarek Behún2-0/+2
Setting DM_FLAG_PRE_RELOC for Armada 3720 clock drivers (TBG and peripheral clocks) makes it possible for serial driver to retrieve clock rates via clk API. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini1-0/+2
various minor sandbox improvements
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan1-3/+3
Replace 'pciaux' with 'pcieaux', including name string and function prefix. The old name string, 'pciaux', might cause an error if PCIe driver is changed to use clk_get_by_name() with 'pcieaux' to get clock. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-01Merge tag 'xilinx-for-v2021.10' of ↵Tom Rini3-0/+198
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases
2021-06-29Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh ↵Tom Rini7-0/+371
into next - V3U Falcon board support
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini1-2/+6
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
2021-06-24clk: renesas: Add R8A779A0 clock tablesHai Pham7-0/+338
Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot
2021-06-24clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2-0/+33
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value from cpg_pll_configs table while PLL{20,21,30,31,4} use different control offset. Introduce new types to handle this and handle those types in the Gen3 clock code. Based on "clk: renesas: Add support for R8A779A0 V3U PLLn" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-23clk: zynq: Add clock wizard driverZhengxun3-0/+198
The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-19Merge tag 'u-boot-rockchip-20210618' of ↵Tom Rini2-0/+2960
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next - New SoC platform support: rk3568; - rockchip pcie Code compile issue fix; - Board fix for rk3399 Khadas Edge; - Add Rockchip NFC driver;
2021-06-18clk: cosmetic change in uclassPatrick Delaunay1-1/+1
Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang2-0/+2960
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-17clk: k210: Move k210 clock out of its own subdirectorySean Anderson5-15/+14
Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Remove bypass driverSean Anderson2-274/+1
This driver no longer serves a purpose now that we have moved away from CCF. Drop it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson1-7/+8
This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Re-add support for setting rateSean Anderson1-5/+84
This adds support for setting clock rates, which was left out of the initial CCF expunging. There are several tricky bits here, mostly related to the PLLS: * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks will be stopped. * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent stopping the CPU while we configure PLL0's rate, ACLK is reparented to IN0 while PLL0 is disabled. * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented, so we instead just disallow changing PLL1's rate after relocation (when we are using the AISRAM). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Implement soc_clk_dumpSean Anderson1-2/+66
Since we are no longer using CCF we cannot use the default soc_clk_dump. Instead, implement our own. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Move pll into the rest of the driverSean Anderson3-594/+601
Now that there no separate PLL driver, we can no longer make the PLL functions static. By moving the PLL driver in with the rest of the clock code, we can make these functions static again. We still keep the pll header for unit testing, but it is pretty reduced. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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