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path: root/drivers/clk/renesas
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2021-06-24clk: renesas: Add R8A779A0 clock tablesHai Pham7-0/+338
Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot
2021-06-24clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2-0/+33
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value from cpg_pll_configs table while PLL{20,21,30,31,4} use different control offset. Introduce new types to handle this and handle those types in the Gen3 clock code. Based on "clk: renesas: Add support for R8A779A0 V3U PLLn" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handlingMarek Vasut1-43/+43
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham3-45/+65
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Introduce enum clk_reg_layoutHai Pham1-0/+6
From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham4-6/+8
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Make reset controller modemr register offset configurableMarek Vasut20-5/+21
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Add support for RPCD2 clockHai Pham2-5/+17
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Fix Realtime Module Stop Control Register offsetsHai Pham1-1/+1
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Fix incorrect return RPC clk_get_rateHai Pham1-1/+1
RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Reinstate RPC clock on R-Car D3/E3Marek Vasut2-0/+18
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12Marek Vasut7-163/+212
Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12Marek Vasut5-9/+6
Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize RZ/G2 tables with Linux 5.12Marek Vasut3-5/+26
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-04-26clk: renesas: Synchronize Gen2 MSTP teardown tablesMarek Vasut3-6/+6
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00 Feb 01, 2016. This corrects the following bits: - added H2 MSTP3[10] SCIF2 - added H2/M2/E2 MSTP7[29] TCON - removed E2 MSTP5[22] Thermal Sensor - removed E2 MSTP10[31,24:22] SRC0, SRC7:9 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-26clk: renesas: Only ever access documented bits in clock driver teardownMarek Vasut7-81/+81
The clock driver used a heavy-handed approach where it turned off all available clocks, while also possibly setting bits which are not documented in the R-Car datasheet. Update the tables so that only the bits which are documented are set or cleared when tearing down the clock driver. Note that the only clock left running before booting Linux are now MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass2-0/+2
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass15-15/+15
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar3-0/+315
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das3-0/+365
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das3-0/+343
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das1-0/+4
Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-07-27Merge tag 'dm-pull-20jul20-take2a' of ↵Tom Rini2-2/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-dm binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-25treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada2-2/+2
Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25clk: renesas: Add R8A774A1 clock tablesAdam Ford4-0/+349
This sync's the clock tables with the official release from Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual v1.00. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2-2/+2
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-20treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada2-2/+2
Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass14-0/+14
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass3-0/+3
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-03-30clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2Marek Vasut1-1/+2
The fdtdec_get_addr() does not take into account values set in #address-cells and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit systems. This is true for most DTs, however there are exceptions. Switch to fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells values into consideration, otherwise the reset controller node register offset is incorrectly parsed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-10clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut3-0/+262
Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut8-130/+215
Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut4-16/+14
Synchronize R-Car Gen2 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut4-19/+346
Add clock tables for R8A77965 from Linux 5.0 , except for the crit, R and Z clock, which are neither used nor supported by the U-Boot clock framework yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Add support for setting MMCIF clock divider on Gen2Marek Vasut1-0/+42
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms. This allows the MMCIF driver to set higher clock rate if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Fix swapped div and mul in debug output on Gen2Marek Vasut1-1/+1
The $div and $mul values were swapped in the debug output, fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Fix SDH clock divider decoding on Gen2Marek Vasut1-5/+9
The gen2_clk_get_sdh_div() function is supposed to look up the $val value read out of the SDCKCR register in the supplied table and return the matching divider value. The current implementation was matching the value from SDCKCR on the divider value in the table, which is wrong. Fix this and rework the function a bit to make it more readable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25clk: rmobile: Drop def_bool per SoCMarek Vasut1-10/+0
Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03clk: renesas: Allow reconfiguring SDHI clock on Gen3Marek Vasut1-7/+3
The SDHI clock must be configured differently for HS200/HS400/SDR104 modes. Add support for reconfiguring the SDHI clock settings into the clock driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14clk: rmobile: Add R8A77995 RPC clockMarek Vasut1-0/+5
Add missing RPC entry into the R8A77995 clock driver tables. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14clk: rmobile: Add R8A77990 RPC clockMarek Vasut1-0/+5
Add missing RPC entry into the R8A77990 clock driver tables. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-02Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-32/+386
2018-06-01clk: renesas: Add R8A77990 E3 clock tablesMarek Vasut3-0/+311
Add clock tables for R8A77990 E3 SoC . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01clk: renesas: Add PE clock handlingMarek Vasut2-6/+40
The PE clock have two parents, add support for picking the correct one and deriving the clock from it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01clk: renesas: Add PLL1 and PLL3 dividersMarek Vasut1-4/+8
Add and use the PLL1 and PLL3 dividers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01clk: renesas: Pass clock rate around as 64bit number internallyMarek Vasut1-25/+31
The PLL rate could be in the GHz range, which could overflow a 32bit data type. Since the hardware is 64bit anyway, pass the clock rates as 64bit number internally to avoid this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01clk: renesas: Fix swapped arguments in debug messageMarek Vasut1-1/+1
The mul and div arguments were reported in reverse order in the debug message, swap them to fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini9-18/+9
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-02clk: renesas: Drop USB extal from the R8A7792 clock driverMarek Vasut1-2/+0
The R8A7792 does not have the USB extal, so drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-21clk: renesas: Minor clean up of the R8A7794 clock driverMarek Vasut1-7/+3
The initconst is not used in U-Boot, drop it. The r8a7794_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-14 11:39:57 +0300