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path: root/include/sbi/sbi_trap_ldst.h
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2025-01-30lib: sbi: move sbi_double_trap_handler() to a dedicated headerClément Léger1-2/+0
We will add new functions to sbi_double_trap.c in order to register an SSE event, split this to a header as part of preparation work. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-12-06lib: sbi_misaligned_ldst: Add handling of vector load/storeNylon Chen1-0/+9
Add misaligned load/store handling for the vector extension to the sbi_misaligned_ldst library. This implementation is inspired from the misaligned_vec_ldst implementation in the riscv-pk project. Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-10-25lib: sbi: add Ssdbltrp ISA extension supportClément Léger1-0/+2
Add Ssdbltrp trap handler support for S-mode double trap handling. If the trap is received while in VS-mode, then the trap is redirected to S-mode. If caught while in HS-mode, then an error is returned to the top trap handler which will panic. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-03-19lib: sbi: Simplify parameters of misaligned and access fault handlersAnup Patel1-8/+4
The struct sbi_trap_context already has the information needed by misaligned load/store and access fault load/store handlers so directly pass struct sbi_trap_context pointer to these functions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Clément Léger <cleger@rivosinc.com>
2024-03-11lib: sbi: abstract out insn decoding to unify mem fault handlersBo Gan1-1/+12
This patch abstracts out the instruction decoding part of misaligned ld/st fault handlers, so it can be reused by ld/st access fault handlers. Also Added lb/lbu/sb decoding. (previously unreachable by misaligned fault) sbi_trap_emulate_load/store is now the common handler which takes a `emu` parameter that is responsible for emulating the misaligned or access fault. The `emu` callback is expected to fixup the fault, and based on the return code of `emu`, sbi_trap_emulate_load/store will: r/wlen => the fixup is successful and regs/mepc needs to be updated. 0 => the fixup is successful, but regs/mepc should be left untouched (this is usually used if `emu` does `sbi_trap_redirect`) -err => failed, sbi_trap_error will be called For now, load/store access faults are blindly redirected. It will be enhanced in the following patches. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11lib: sbi: change prototype of sbi_misaligned_load/store_handlerBo Gan1-4/+5
This simplifies both handlers such that when the handler needs to redirect the original trap, it's readily available. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11include: sbi: rename sbi_misaligned_ldst.h to sbi_trap_ldst.hBo Gan1-0/+23
Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>