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2025-02-19include: sbi: Add SBI_ERR_DENIED_LOCKEDClément Léger2-1/+3
Add SBI_ERR_DENIED_LOCKED and set it as the SBI_LAST_ERR which was wrongly set to SBI_ERR_BAD_RANGE. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-02-19lib: sbi: Fix non-root domain startupAnup Patel1-2/+5
Currently, the sbi_sse_init() in cold boot path is called after sbi_domain_finalize() so boot HART of non-root domains will start before SSE cold boot init which can cause warm boot of such HARTs to crash in sbi_sse_init(). To address the above issue, factor-out the non-root domain startup from sbi_domain_finalize() function as a separate sbi_domain_startup() function which can be called after sbi_sse_init() in cold boot path. Fixes: 93f7d819fdeb ("lib: sbi: sse: allow adding new events") Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2025-02-13lib: sbi: Update MPXY framework and SBI extension as per latest specAnup Patel2-12/+15
The latest SBI 3.0 spec defines a new sbi_mpxy_get_shmem_size() function and simplifies sbi_mpxy_set_shmem() function so update the MPXY framework and SBI extension accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2025-02-12include: sbi: Align SBI trap registers to a nice boundaryRaj Vishwanathan1-2/+5
Align SBI_TRAP_CONTEXT_SIZE to a multiple of 16 bytes. If it is not aligned to 16 bytes for RV64, it can create performance problems. Aligning it correctly can fix the performance issues. Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-01-30lib: sbi: sse: allow adding new eventsClément Léger1-4/+4
In order to allow events to be dynamically added, remove the existing static array of events and use a simply linked list of supported events. This allows us to move the cb_ops into this list and associated it with an event_id. Drivers can now register cb_ops before bringing up the sse core to handle additional events (platform ones for instance). sbi_sse_init() now allocates as many events as present in the linked list. Events can now be added with sbi_sse_add_event() which allows to add new supported events with some callback operations if any. If an event is not to be supported, then sbi_sse_add_event() should not be called. This approach currently consider that local events are to be supported on all harts (ie, they all support the same ISA or dependencies). If per-hart event availability needs to be supported, then, an is_supported() callback could be added later and called for each hart. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2025-01-30include: lib: add a simple singly linked list implementationClément Léger1-0/+33
Add a simple singly linked list implementation when double linked list are not needed. This allows to easily have statically defined linked list that can be extended at runtime. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-01-30lib: sbi: move sbi_double_trap_handler() to a dedicated headerClément Léger2-2/+20
We will add new functions to sbi_double_trap.c in order to register an SSE event, split this to a header as part of preparation work. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-01-30lib: sbi: pmu: fix usage of sbi_pmu_irq_bit()Clément Léger1-0/+3
While sbi_pmu_irq_bit() was used to delegate irq to S-mode, LCOFIP usage was still hardcoded in various places. This led to change the returned value of sbi_pmu_irq_bit() to be a bit number rather than a bit mask since it returns an 'int' and we need to obtain the bit number itself to handle it in the IRQs handlers. Add a similar function to return the irq mask which can also be used where the mask is required rather than the bit itself. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2024-12-24include: Bump-up version to 1.6v1.6Anup Patel1-1/+1
Update the OpenSBI version to 1.6 as part of release preparation. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-12-22lib: sbi: Print list of available SBI extensions at boot-timeAnup Patel1-0/+6
Add boot-time prints for list of available standard and experimental SBI extensions. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-12-21include: sbi: Fix compiling with C23 enabled compilersMichael Neuling1-4/+6
C23 pre-defines bool so we need to gate our defines. Signed-off-by: Michael Neuling <michaelneuling@tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-12-15lib: sbi: fix GLOBAL_PLAT_DEFINEClément Léger1-2/+2
Fix GLOBAL_PLAT_0_START/END definitions. The specification states that the beginning of the range is 0xc000 and the end is 0xffff. Reported-by: Andrew Jones <andrew.jones@linux.dev> Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-12-06lib: sbi_misaligned_ldst: Add handling of vector load/storeNylon Chen2-1/+393
Add misaligned load/store handling for the vector extension to the sbi_misaligned_ldst library. This implementation is inspired from the misaligned_vec_ldst implementation in the riscv-pk project. Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-12-06lib: sbi: Implement SBI MPXY extensionAnup Patel1-0/+10
Implement the SBI MPXY extension which provides an SBI interface to the supervisor software for send messages via MPXY framework. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Co-developed-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-12-06lib: sbi: Add SBI Message Proxy (MPXY) frameworkRahul Pathak4-7/+210
Introduce SBI Message Proxy (MPXY) framework which allows platform specific code or drivers to register message protocol specific channels. This framework enables the supervisor software to send messages belonging to different message protocols via OpenSBI firmware. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Co-developed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Co-developed-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-12-06lib: sbi: Add optional resume address to hart suspendSubrahmanya Lingappa1-1/+5
Add an optional resume address to the platform specific hart suspend call. Signed-off-by: Subrahmanya Lingappa <slingappa@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-12-02lib: sbi_pmu: Implement SBI PMU event info functionAtish Patra1-0/+2
Allow the supervisor software to query about the event using the new function. This supports both firmware and hardware events. The hardware event presence is verified hw_event_map which is populated via PMU device tree node. The firmware event presence is checked through event validation function which should take care of both standard and platform firmware events. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-12-02lib: sbi_pmu: Add SBI PMU event info function details.Atish Patra1-0/+9
The SBI v3.0 introduced a new function to query about the events without invoking CFG_MATCH. This allows supervisor software to identify which events are supported on the platform with single SBI call instead of a CFG_MATCH for each event. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-12-02lib: sbi_pmu: PMU raw event v2 supportAtish Patra1-0/+2
As per the updated ISA specification and SBI PMU v3.0, lower 56 bits are available for the platform to implement mhpmeventX encoding. Implement the PMU raw event V2 support defined in SBI v3.0 which allows more bits for platforms to encode the raw events. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-28lib: sbi_irqchip: Set the IRQ handler when registering a chipSamuel Holland1-10/+3
In addition to saving some code size, this moves the decision about setting the top-level external interrupt handler to the irqchip core, not the specific driver, which would be needed to support chained interrupt handlers. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-28platform: Drop irqchip warm init and exit hooksSamuel Holland1-20/+5
Now that driver lifecycle is managed from within the SBI irqchip core, platforms need only to initialize the driver once during cold init. Remove the remaining platform hooks that are no longer used. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-28lib: sbi_irqchip: Call driver warm_init from SBI coreSamuel Holland1-0/+3
Currently, each platform keeps track of which irqchip driver is in use and calls its warm init function. Since the generic platform may use multiple irqchip drivers, it has logic to track an array of drivers. The code is simplified and made common across platforms by treating warm init and exit as properties of the driver, not the platform. Then the platform's only role is to select and prepare a driver during cold boot. For now, only add a .warm_init hook, since none of the existing drivers need an .exit hook. It could be added in the future if needed. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-28lib: sbi_irqchip: Register devices during cold initSamuel Holland1-0/+10
Have the SBI irqchip core keep track of registered irqchip devices. This is useful for any callbacks the irqchip driver may have, such as for warm initialization, the external interrupt handler function, and any future support for handling external interrupts (beyond IPIs) in M-mode. This improves on the tracking done in fdt_irqchip.c, as it tracks device instances, not just drivers, so callbacks can target a specific device. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-11platform: Drop IPI warm init and exit hooksSamuel Holland1-20/+5
Now that the SBI IPI core clears IPIs at warm boot in a generic way, none of the drivers or platforms use these hooks, and we can remove them. Platforms need only to initialize the driver once during cold init. If other hooks are needed in the future, they can be added to struct sbi_ipi_device. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-11lib: sbi_ipi: Make .ipi_clear always target the current hartSamuel Holland1-3/+3
All existing users of this operation target the current hart, and it seems unlikely that a future user will need to clear the pending IPI status of a remote hart. Simplify the logic by changing .ipi_clear (and its wrapper sbi_ipi_raw_clear()) to always operate on the current hart. This incidentally fixes a bug introduced in commit 78c667b6fc07 ("lib: sbi: Prefer hartindex over hartid in IPI framework"), which changed the .ipi_clear parameter from a hartid to a hart index, but failed to update the warm_init functions to match. Fixes: 78c667b6fc07 ("lib: sbi: Prefer hartindex over hartid in IPI framework") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-11include: sbi: Fix typo errorZhang RunMin1-1/+1
Fix typo in comments describing SBI_SCRATCH_FW_HEAP_SIZE_OFFSET. Signed-off-by: Zhang RunMin <runmin.zhang@ingenic.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-11platform: ensure enough heap size with debug triggers extensionInochi Amaoto1-1/+1
DBTR introduce a big heap allocation to store hart state, this is allocated percpu and needs big space when CPU number is high. Increase the percpu part to fix this problem, and decrease the fixed part to avoid too big heap size. Fixes: 97f234f (lib: sbi: Introduce the SBI debug triggers extension support) Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-05platform: Drop timer warm init and exit hooksSamuel Holland1-20/+5
Now that driver lifecycle is managed from within the SBI timer core, platforms need only to initialize the driver once during cold init. Remove the remaining platform hooks that are no longer used. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-11-05lib: sbi_timer: Call driver warm_init from SBI coreSamuel Holland1-0/+3
Currently, the platform's timer device is tracked in two places: the core SBI implementation has `timer_dev`, and the FDT timer layer has `current_driver`. The latter is used for warm initialization of the timer device. However, this warm init is not specific to FDT-based platforms; other platforms call exactly the same functions from the same point in the boot sequence. The code is simplified and made common across platforms by treating warm init and exit as properties of the driver, not the platform. Then the platform's only role is to select and prepare a driver during cold boot. For now, only add a .warm_init hook, since none of the existing drivers need an .exit hook. It could be added in the future if needed. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-10-28include: sbi: Optimize reads of mhartid and mscratchSamuel Holland2-2/+10
csr_read() is marked as volatile and clobbering memory, which is generally the safe thing to do. However, these two CSRs do not have any side effects, and the values returned do not change between calls. The compiler can generate better code if we allow it to reorder calls to these functions and cache the return value. Introduce csr_read_relaxed() for this use case. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-10-25lib: sbi: add Smdbltrp ISA extension supportClément Léger1-1/+3
Add support for the Smdbltrp[1] ISA extension. First thing to do is clearing MDT on entry after setting the first MTVEC (since MDT is reset to 1). Additionally, during trap handling, clear MDT once all critical CSRs have been saved and in return path, restore MSTATUS/H before restoring MEPC to avoid taking another trap which would clobber it. Link: https://github.com/riscv/riscv-double-trap/releases/download/v0.56/riscv-double-trap.pdf [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: implement firmware feature SBI_FWFT_DOUBLE_TRAPClément Léger1-1/+2
Add support for double trap firmware feature. Link: https://lists.riscv.org/g/tech-prs/message/985 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: fwft: factorize menvcfg read/writeClément Léger1-3/+6
MENVCFG access will be used as well for double trap, landing pad and shadow stack fwft support. Factorize that in a common function. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: send a double trap SSE event to supervisorClément Léger1-0/+1
In case the double trap handler is called and the double trap happened in supervisor mode, send a double trap SSE event. NOTE: this commit depends on the ratification of the new SSE event id for double trap [1]. Link: https://lists.riscv.org/g/tech-prs/message/985 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: add Ssdbltrp ISA extension supportClément Léger3-1/+7
Add Ssdbltrp trap handler support for S-mode double trap handling. If the trap is received while in VS-mode, then the trap is redirected to S-mode. If caught while in HS-mode, then an error is returned to the top trap handler which will panic. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: factorize previous mode computationClément Léger1-0/+5
Previous privilege mode retrieval from mstatus is done at different places, factorize it rather than copy/pasting it again. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: factorize previous virtualization mode read from regsClément Léger1-0/+9
The same pattern is used at multiple places to verify in which mode the exception was actually taken. Factorize it. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi: Add support to mask/unmask SSE eventsHimanshu Chauhan2-0/+4
Add functions to globally mask/unmask supervisor software events on the calling hart. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-10-25lib: sbi_domain: Use domain data support for per-domain hart contextAnup Patel2-48/+10
The per-domain hartindex_to_context_table[] is yet another per-domain data required for implementing hart entry into (or exit from) domain. Use the recently added domain data support for per-domain hart context so that a dedicated hartindex_to_context_table[] in struct sbi_domain is not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2024-10-25lib: sbi: Introduce domain dataAnup Patel2-0/+96
Different parts of OpenSBI require their own per-domain data so introduce domain data (or sbi_domain_data) which can be registered by any part of OpenSBI. Using the domain data, the domain framework will create a data pointer for every domain which can be used to maintain some per-domain state. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2024-10-25include: sbi: Remove cyclic include in sbi_domain_context.hAnup Patel1-1/+2
The sbi_domain_context.h includes sbi_domain.h and the sbi_domain.h also includes sbi_domain_context.h. Remove this cyclic include in sbi_domain_context.h. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-10-25lib: sbi_domain: Make sbi_domain_root_add_memregion() as local functionAnup Patel1-10/+0
The sbi_domain_root_add_memregion() is only used within sbi_domain implementation so rename and make it a local function. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2024-09-27include: sbi: Don't unconditionally define '__always_inline'Elyes Haouas1-0/+3
Update __always_inline macro define to fix opensbi upstream build for coreboot. Refer, https://qa.coreboot.org/job/coreboot-gerrit/257449/testReport/junit/(root)/clang/EMULATION_QEMU_RISCV_RV64_/ Closes: https://github.com/riscv-software-src/opensbi/issues/366 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2024-09-26lib: sbi: Remove unused hartid parametersSamuel Holland1-1/+1
None of these functions use their hartid parameter. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Update sbi_{entry,init}_count() to take a hart indexSamuel Holland1-2/+2
All callers already have the hartindex available, so this removes a hartid to hartindex conversion. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Update sbi_domain_is_assigned_hart() to take a hart indexSamuel Holland1-2/+2
This removes redundant hartid to hartindex conversions from four call sites and provides a net reduction in code size. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Use sbi_hartmask in sbi_hsm_hart_interruptible_mask()Samuel Holland3-7/+19
This removes several hartid/hartindex conversions, as well as two loops through the mask for broadcast IPIs. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-26lib: sbi: Update __sbi_hsm_hart_get_state() to take a hart indexSamuel Holland1-1/+1
This removes some hartindex conversions in sbi_system_suspend(), but is mostly intended to support refactoring sbi_hsm_hart_interruptible_mask() to work exclusively with struct sbi_hartmask. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25lib: sbi: Use current_hartindex() where possibleSamuel Holland2-5/+4
This avoids calls to the expensive sbi_hartid_to_hartindex() function and also makes the firmware smaller. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-25include: sbi: Store the hart index in struct sbi_scratchSamuel Holland1-1/+9
This is a more efficient way to get the index of the current hart than calling a function to loop through the hartindex -> hartid lookup table. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 20:38:32 +0300