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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2022-03-07drm/i915/psr: Set "SF Partial Frame Enable" also on full updateJouni Högander1-0/+1
2022-01-31drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for referenceUmesh Nerlige Ramappa1-1/+2
2022-01-25drm/i915: Flush TLBs before releasing backing storeTvrtko Ursulin1-0/+11
2022-01-17drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza1-2/+6
2021-12-23Merge tag 'drm-intel-gt-next-2021-12-23' of git://anongit.freedesktop.org/drm...Dave Airlie1-0/+4
2021-12-21drm/i915/guc: Request RP0 before loading firmwareVinay Belgaumkar1-0/+4
2021-12-17Merge tag 'drm-intel-next-2021-12-14' of ssh://git.freedesktop.org/git/drm/dr...Dave Airlie1-19/+29
2021-12-10Merge tag 'drm-intel-gt-next-2021-12-09' of git://anongit.freedesktop.org/drm...Dave Airlie1-16/+140
2021-12-07drm/i915/display/dg2: Set CD clock squashing registersMika Kahola1-0/+8
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula1-0/+1
2021-12-03drm/i915: Rename PLANE_CUS_CTL Y plane bitsVille Syrjälä1-4/+4
2021-12-03drm/i915: Rename plane YUV order bitsVille Syrjälä1-7/+7
2021-12-03drm/i915: Get rid of the 64bit PLANE_CC_VAL mmioVille Syrjälä1-6/+6
2021-12-03drm/i915/dg2: Add Wa_14010547955Matt Roper1-2/+3
2021-11-24Revert "drm/i915/dg2: Tile 4 plane format support"Stanislav Lisovskiy1-1/+0
2021-11-23drm/i915/dg2: Tile 4 plane format supportStanislav Lisovskiy1-0/+1
2021-11-22Merge drm/drm-next into drm-intel-gt-nextTvrtko Ursulin1-1/+3
2021-11-19drm/i915: Clean up CRC register definesVille Syrjälä1-36/+41
2021-11-19drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bitsVille Syrjälä1-47/+47
2021-11-19drm/i915: Clean up FPGA_DBG/CLAIM_ER bitsVille Syrjälä1-4/+4
2021-11-17drm/i915/dsi/xelpd: Fix the bit mask for wakeup GBVandita Kulkarni1-1/+3
2021-11-15drm/i915/dsi/xelpd: Fix the bit mask for wakeup GBVandita Kulkarni1-1/+3
2021-11-11drm/i915/dg2: Program recommended HW settingsMatt Roper1-0/+9
2021-11-11drm/i915/dg2: Add initial gt/ctx/engine workaroundsMatt Roper1-17/+77
2021-11-11drm/i915/xehpsdv: Add initial workaroundsStuart Summers1-0/+53
2021-11-11drm/i915: Relocate FBC_LLC_READ_CTRLVille Syrjälä1-3/+3
2021-11-11drm/i915/fbc: Finish polishing FBC1 registersVille Syrjälä1-26/+36
2021-11-11drm/i915/fbc: Clean up all register definesVille Syrjälä1-42/+43
2021-11-11drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASKVille Syrjälä1-2/+1
2021-11-02drm/i915/display: program audio CDCLK-TS for keepalivesKai Vehmanen1-0/+4
2021-10-29drm/i915/adlp: Implement workaround 16013190616José Roberto de Souza1-3/+4
2021-10-28drm/i915/pmu: Connect engine busyness stats from GuC to pmuUmesh Nerlige Ramappa1-0/+2
2021-10-26drm/i915/display: Wait PSR2 get out of deep sleep to update pipeJosé Roberto de Souza1-5/+5
2021-10-19drm/i915: Move LPT PCH readout codeVille Syrjälä1-2/+0
2021-10-18drm/i915: Don't propagate the gen split confusion furtherRodrigo Vivi1-1/+1
2021-10-14drm/i915: Remove memory frequency calculationJosé Roberto de Souza1-8/+0
2021-10-14drm/i915: Add all per-lane register definitions for icl combo phyVille Syrjälä1-6/+4
2021-10-14drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuffVille Syrjälä1-1/+0
2021-10-12Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-3/+81
2021-10-11Merge tag 'drm-intel-gt-next-2021-10-08' of git://anongit.freedesktop.org/drm...Dave Airlie1-3/+81
2021-10-04drm/i915: Extend the async flip VT-d w/a to skl/bxtVille Syrjälä1-0/+5
2021-10-04drm/i915/pxp: black pixels on pxp disabledAnshuman Gupta1-0/+46
2021-10-04drm/i915/pxp: Add plane decryption supportAnshuman Gupta1-0/+1
2021-10-04drm/i915/pxp: Implement PXP irq handlerHuang, Sean Z1-0/+1
2021-10-04drm/i915/reg: add AUD_TCA_DP_2DOT0_CTRL registersJani Nikula1-0/+5
2021-09-29drm/i915/gen11: Disable cursor clock gating in HDR modeTejas Upadhyay1-0/+1
2021-09-24drm/i915/fbc: Align FBC segments to 512B on glk+Ville Syrjälä1-0/+4
2021-09-21drm/i915/xehp: Check new fuse bits for SFC availabilityMatt Roper1-2/+2
2021-09-20drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b modeJani Nikula1-1/+1
2021-09-17drm/i915/display/adlp: Add new PSR2 workaroundsJosé Roberto de Souza1-0/+4
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-03 13:49:40 +0300