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path: root/drivers/cxl
AgeCommit message (Expand)AuthorFilesLines
2024-01-13cxl/core: use sysfs_emit() for attr's _show()Shiyang Ruan1-1/+1
2024-01-10Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams4-138/+124
2024-01-10cxl/pci: Register for and process CPER eventsIra Weiny3-13/+89
2024-01-10cxl/events: Create a CXL event unionIra Weiny2-23/+17
2024-01-10cxl/events: Separate UUID from event structuresIra Weiny1-1/+1
2024-01-10cxl/events: Remove passing a UUID to known event tracesIra Weiny2-15/+19
2024-01-10cxl/events: Create common event UUID definesIra Weiny2-27/+27
2024-01-06Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams3-26/+14
2024-01-06Merge branch 'for-6.8/cxl-misc' into for-6.8/cxlDan Williams1-1/+1
2024-01-06Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams6-27/+44
2024-01-06cxl/events: Promote CXL event structures to a core headerIra Weiny1-89/+1
2024-01-06cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_pr...Dave Jiang1-3/+2
2024-01-06cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_brid...Dave Jiang1-5/+3
2024-01-06cxl: Fix device reference leak in cxl_port_perf_data_calculate()Dave Jiang1-2/+5
2024-01-06cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang6-23/+28
2024-01-06cxl: Introduce put_cxl_root() helperDave Jiang2-0/+12
2024-01-05cxl/port: Fix missing target list lockDan Williams2-17/+7
2024-01-05cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying1-1/+1
2024-01-04cxl/region: fix x9 interleave typoJim Harris1-1/+1
2024-01-04cxl/trace: Pass UUID explicitly to event tracesIra Weiny2-18/+18
2024-01-02Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams17-39/+1009
2024-01-02cxl/region: use %pap format to print resource_size_tRandy Dunlap1-2/+2
2023-12-25cxl/region: Add dev_dbg() detail on failure to allocate HPA spaceAlison Schofield1-2/+3
2023-12-23cxl: Check qos_class validity on memdev probeDave Jiang1-0/+103
2023-12-23cxl: Export sysfs attributes for memory device QoS classDave Jiang1-6/+61
2023-12-23cxl: Store QTG IDs and related info to the CXL memory device contextDave Jiang3-0/+92
2023-12-23cxl: Compute the entire CXL path latency and bandwidth dataDave Jiang1-1/+58
2023-12-23cxl: Add helper function that calculate performance data for downstream portsDave Jiang2-0/+78
2023-12-23cxl: Store the access coordinates for the generic portsDave Jiang2-0/+27
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang5-0/+61
2023-12-23cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang3-13/+193
2023-12-23cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang3-0/+104
2023-12-23cxl: Add callback to parse the DSLBIS subtable from CDATDave Jiang1-2/+100
2023-12-23cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang5-0/+99
2023-12-19cxl: Fix unregister_region() callback parameter assignmentDave Jiang1-4/+4
2023-12-15cxl/pmu: Ensure put_device on pmu devicesIra Weiny1-1/+1
2023-12-09cxl/cdat: Free correct buffer on checksum errorIra Weiny1-7/+6
2023-12-08cxl/hdm: Fix dpa translation lockingDan Williams2-4/+3
2023-12-07cxl: Add Support for Get TimestampDavidlohr Bueso2-0/+2
2023-11-30cxl/memdev: Hold region_rwsem during inject and clear poison opsAlison Schofield1-2/+16
2023-11-30cxl/core: Always hold region_rwsem while reading poison listsAlison Schofield2-6/+8
2023-11-23cxl/hdm: Fix a benign lockdep splatDave Jiang1-0/+2
2023-11-03cxl/pci: Change CXL AER support check to use native AERTerry Bowman1-2/+2
2023-11-01cxl/hdm: Remove broken error pathDan Williams2-17/+10
2023-11-01cxl/hdm: Fix && vs || bugDan Carpenter1-1/+1
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams5-6/+40
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams4-5/+11
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams5-12/+60
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams10-129/+406
2023-10-28cxl: Add support for reading CXL switch CDAT tableDave Jiang2-5/+20
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