Age | Commit message (Expand) | Author | Files | Lines |
2023-06-30 | cxl: Fix one kernel-doc comment | Yang Li | 1 | -1/+1 |
2023-06-28 | cxl/pci: Use correct flag for sanitize polling | Davidlohr Bueso | 1 | -1/+1 |
2023-06-26 | Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl | Dan Williams | 12 | -291/+443 |
2023-06-26 | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl | Dan Williams | 10 | -7/+224 |
2023-06-26 | perf: CXL Performance Monitoring Unit driver | Jonathan Cameron | 1 | -0/+13 |
2023-06-26 | Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxl | Dan Williams | 2 | -46/+72 |
2023-06-26 | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl | Dan Williams | 16 | -445/+515 |
2023-06-26 | Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxl | Dan Williams | 4 | -0/+395 |
2023-06-26 | Merge branch 'for-6.5/cxl-background' into for-6.5/cxl | Dan Williams | 6 | -21/+434 |
2023-06-26 | cxl: add a firmware update mechanism using the sysfs firmware loader | Vishal Verma | 4 | -0/+395 |
2023-06-26 | cxl/mem: Support Secure Erase | Davidlohr Bueso | 3 | -1/+34 |
2023-06-26 | cxl/mem: Wire up Sanitization support | Davidlohr Bueso | 4 | -0/+132 |
2023-06-26 | cxl/mbox: Add sanitization handling machinery | Davidlohr Bueso | 3 | -3/+91 |
2023-06-26 | cxl/mem: Introduce security state sysfs file | Davidlohr Bueso | 3 | -0/+46 |
2023-06-26 | cxl/mbox: Allow for IRQ_NONE case in the isr | Davidlohr Bueso | 1 | -2/+4 |
2023-06-26 | Revert "cxl/port: Enable the HDM decoder capability for switch ports" | Dan Williams | 3 | -33/+9 |
2023-06-26 | cxl/memdev: Formalize endpoint port linkage | Dan Williams | 4 | -5/+8 |
2023-06-26 | cxl/pci: Unconditionally unmask 256B Flit errors | Dan Williams | 1 | -16/+2 |
2023-06-26 | cxl/region: Manage decoder target_type at decoder-attach time | Dan Williams | 1 | -0/+12 |
2023-06-26 | cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM | Dan Williams | 2 | -10/+27 |
2023-06-26 | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM} | Dan Williams | 5 | -12/+13 |
2023-06-26 | cxl/memdev: Make mailbox functionality optional | Dan Williams | 3 | -1/+28 |
2023-06-26 | cxl/mbox: Move mailbox related driver state to its own data structure | Dan Williams | 7 | -271/+312 |
2023-06-26 | cxl: Remove leftover attribute documentation in 'struct cxl_dev_state' | Dan Williams | 1 | -1/+0 |
2023-06-26 | cxl: Fix kernel-doc warnings | Dan Williams | 1 | -3/+3 |
2023-06-26 | cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output | Dan Williams | 2 | -6/+6 |
2023-06-25 | cxl/region: Fix state transitions after reset failure | Dan Williams | 1 | -11/+15 |
2023-06-25 | cxl/region: Flag partially torn down regions as unusable | Dan Williams | 2 | -0/+20 |
2023-06-25 | cxl/region: Move cache invalidation before region teardown, and before setup | Dan Williams | 2 | -36/+38 |
2023-06-25 | cxl/port: Store the downstream port's Component Register mappings in struct c... | Robert Richter | 2 | -0/+13 |
2023-06-25 | cxl/port: Store the port's Component Register mappings in struct cxl_port | Robert Richter | 2 | -0/+29 |
2023-06-25 | cxl/pci: Early setup RCH dport component registers from RCRB | Robert Richter | 4 | -18/+57 |
2023-06-25 | cxl/mem: Prepare for early RCH dport component register setup | Robert Richter | 1 | -5/+4 |
2023-06-25 | cxl/regs: Remove early capability checks in Component Register setup | Robert Richter | 3 | -9/+6 |
2023-06-25 | cxl/port: Remove Component Register base address from struct cxl_dport | Robert Richter | 2 | -3/+0 |
2023-06-25 | cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port | Robert Richter | 1 | -28/+63 |
2023-06-25 | cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() | Robert Richter | 1 | -45/+45 |
2023-06-25 | cxl/pci: Refactor component register discovery for reuse | Terry Bowman | 3 | -74/+83 |
2023-06-25 | cxl/core/regs: Add @dev to cxl_register_map | Robert Richter | 4 | -24/+31 |
2023-06-25 | cxl: Rename 'uport' to 'uport_dev' | Dan Williams | 7 | -63/+71 |
2023-06-25 | cxl: Rename member @dport of struct cxl_dport to @dport_dev | Robert Richter | 3 | -14/+14 |
2023-06-25 | cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability | Dan Williams | 4 | -7/+15 |
2023-06-25 | cxl/acpi: Probe RCRB later during RCH downstream port creation | Robert Richter | 6 | -50/+61 |
2023-05-30 | cxl/pci: Find and register CXL PMU devices | Jonathan Cameron | 9 | -1/+155 |
2023-05-30 | cxl: Add functions to get an instance of / count regblocks of a given type | Jonathan Cameron | 2 | -6/+56 |
2023-05-26 | cxl: Explicitly initialize resources when media is not ready | Dave Jiang | 1 | -6/+11 |
2023-05-23 | cxl/mbox: Add background cmd handling machinery | Davidlohr Bueso | 4 | -1/+106 |
2023-05-23 | cxl/pci: Introduce cxl_request_irq() | Davidlohr Bueso | 1 | -16/+23 |
2023-05-23 | cxl/pci: Allocate irq vectors earlier during probe | Davidlohr Bueso | 1 | -4/+4 |
2023-05-20 | cxl/port: Fix NULL pointer access in devm_cxl_add_port() | Robert Richter | 1 | -4/+3 |