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path: root/drivers/cxl/core/pci.c
AgeCommit message (Expand)AuthorFilesLines
2023-05-13cxl: Add missing return to cdat read error pathDave Jiang1-0/+1
2023-04-23cxl/port: Fix port to pci device assumptions in read_cdat_data()Dan Williams1-6/+7
2023-04-18cxl/pci: Rightsize CDAT response allocationLukas Wunner1-17/+19
2023-04-18cxl/pci: Simplify CDAT retrieval error pathDave Jiang1-11/+12
2023-04-18cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner1-22/+5
2023-04-18cxl/pci: Use synchronous API for DOELukas Wunner1-44/+22
2023-04-04cxl/pci: Handle excessive CDAT lengthLukas Wunner1-0/+3
2023-04-04cxl/pci: Handle truncated CDAT entriesLukas Wunner1-4/+9
2023-04-04cxl/pci: Handle truncated CDAT headerLukas Wunner1-1/+1
2023-03-21cxl/pci: Fix CDAT retrieval on big endianLukas Wunner1-13/+13
2023-02-17Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams1-6/+2
2023-02-17cxl/trace: Standardize device information outputIra Weiny1-6/+2
2023-02-15Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-107/+93
2023-02-15cxl/pci: Remove locked check for dvsec_range_allowed()Dave Jiang1-2/+0
2023-02-15cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-3/+6
2023-02-15cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+1
2023-02-15cxl/pci: Refactor cxl_hdm_decode_init()Dave Jiang1-81/+54
2023-02-15cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-11/+7
2023-02-15cxl/pci: Break out range register decoding from cxl_hdm_decode_init()Dave Jiang1-24/+40
2023-02-11Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-5/+0
2023-02-11kernel/range: Uplevel the cxl subsystem's range_contains() helperDan Williams1-5/+0
2023-02-07Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-0/+115
2023-01-05cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+112
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-2/+1
2022-12-04cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-2/+1
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter1-2/+0
2022-07-20cxl/port: Read CDAT tableIra Weiny1-0/+173
2022-07-10cxl/core: Drop ->platform_res attribute for root decodersDan Williams1-7/+1
2022-05-20cxl/port: Enable HDM Capability after validating DVSEC RangesDan Williams1-15/+152
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams1-29/+10
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams1-8/+7
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams1-7/+75
2022-05-19cxl/mem: Skip range enumeration if mem_enable clearDan Williams1-0/+2
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-0/+129
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams1-0/+48
2022-02-09cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-5/+2
2022-02-09cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-2/+0
2022-02-09cxl/core: Generalize dport enumeration in the coreDan Williams1-0/+101
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