starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-07-30	clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock regi...	Lad Prabhakar	1	-28/+17
2024-07-30	clk: renesas: rzg2l-cpg: Use devres API to register clocks	Lad Prabhakar	1	-6/+20
2024-04-25	clk: renesas: rzg2l: Extend power domain support	Claudiu Beznea	1	-14/+185
2023-12-13	clk: renesas: rzg2l: Check reset monitor registers	Claudiu Beznea	1	-15/+44
2023-11-27	clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()	Claudiu Beznea	1	-23/+15
2023-10-12	clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()	Claudiu Beznea	1	-1/+1
2023-10-10	clk: renesas: Add minimal boot support for RZ/G3S SoC	Claudiu Beznea	1	-0/+6
2023-10-10	clk: renesas: rzg2l: Add divider clock for RZ/G3S	Claudiu Beznea	1	-0/+186
2023-10-10	clk: renesas: rzg2l: Refactor SD mux driver	Claudiu Beznea	1	-42/+108
2023-10-05	clk: renesas: rzg2l: Add struct clk_hw_data	Claudiu Beznea	1	-18/+34
2023-10-05	clk: renesas: rzg2l: Add support for RZ/G3S PLL	Claudiu Beznea	1	-4/+45
2023-10-05	clk: renesas: rzg2l: Remove critical area	Claudiu Beznea	1	-4/+1
2023-10-05	clk: renesas: rzg2l: Fix computation formula	Claudiu Beznea	1	-6/+6
2023-10-05	clk: renesas: rzg2l: Trust value returned by hardware	Claudiu Beznea	1	-7/+1
2023-10-05	clk: renesas: rzg2l: Lock around writes to mux register	Claudiu Beznea	1	-10/+13
2023-10-05	clk: renesas: rzg2l: Wait for status bit of SD mux before continuing	Claudiu Beznea	1	-7/+10
2023-09-18	clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields	Claudiu Beznea	1	-5/+5
2023-09-18	clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()	Claudiu Beznea	1	-3/+2
2023-09-18	clk: renesas: rzg2l: Use core->name for clock name	Claudiu Beznea	1	-1/+1
2023-08-31	Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...	Stephen Boyd	1	-9/+2
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	1	-2/+1
2023-07-11	clk: renesas: rzg2l: Simplify .determine_rate()	Christophe JAILLET	1	-7/+1
2023-06-05	clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+5
2023-05-23	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	Biju Das	1	-4/+2
2023-04-13	clk: renesas: remove MODULE_LICENSE in non-modules	Nick Alcock	1	-1/+0
2022-10-28	clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM	Lad Prabhakar	1	-15/+24
2022-10-26	clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc	Lad Prabhakar	1	-1/+1
2022-10-17	clk: renesas: rzg2l: Fix typo in function name	Lad Prabhakar	1	-3/+3
2022-10-17	clk: renesas: rzg2l: Support sd clk mux round operation	Biju Das	1	-1/+1
2022-06-07	clk: renesas: rzg2l: Fix reset status function	Biju Das	1	-1/+1
2022-05-06	clk: renesas: Add RZ/V2M support using the rzg2l driver	Phil Edworthy	1	-0/+6
2022-05-05	clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg	Phil Edworthy	1	-1/+9
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	1	-1/+7
2022-05-05	clk: renesas: rzg2l: Add DSI divider clk support	Biju Das	1	-0/+125
2022-05-05	clk: renesas: rzg2l: Add PLL5_4 clk mux support	Biju Das	1	-0/+93
2022-05-05	clk: renesas: rzg2l: Add FOUTPOSTDIV clk support	Biju Das	1	-0/+212
2022-04-13	clk: renesas: Add support for RZ/G2UL SoC	Biju Das	1	-0/+6
2022-04-13	clk: renesas: rzg2l: Simplify multiplication/shift logic	Geert Uytterhoeven	1	-1/+1
2022-04-04	clk: renesas: rzg2l: Remove unused notifiers	Phil Edworthy	1	-2/+0
2022-02-10	clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC	Biju Das	1	-0/+6
2021-11-19	clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()	Lad Prabhakar	1	-2/+1
2021-11-19	clk: renesas: rzg2l: Check return value of pm_genpd_init()	Lad Prabhakar	1	-1/+13
2021-11-15	clk: renesas: rzg2l: Add missing kerneldoc for resets	Geert Uytterhoeven	1	-0/+1
2021-10-08	clk: renesas: rzg2l: Add SDHI clk mux support	Biju Das	1	-0/+118
2021-09-24	clk: renesas: rzg2l: Add support to handle coupled clocks	Biju Das	1	-0/+71
2021-09-24	clk: renesas: rzg2l: Add support to handle MUX clocks	Biju Das	1	-0/+23
2021-09-24	clk: renesas: rzg2l: Fix clk status function	Biju Das	1	-1/+1
2021-07-19	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	Geert Uytterhoeven	1	-0/+750