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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2025-07-05clk: starfive: jh7100: Keep more clocks aliveEmil Renner Berthing1-9/+10
2025-05-30Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds66-259/+6189
2025-05-29Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' ...Stephen Boyd31-95/+594
2025-05-29Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' int...Stephen Boyd10-66/+3015
2025-05-29Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup...Stephen Boyd25-98/+2580
2025-05-18Merge tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd2-21/+48
2025-05-18clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocksTaniya Das1-0/+4
2025-05-18clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750Taniya Das2-1/+4
2025-05-18clk: qcom: rpmh: make clkaN optionalPengyu Luo1-0/+11
2025-05-18clk: qcom: Add support for Camera Clock Controller on QCS8300Imran Shaik1-5/+98
2025-05-15clk: rockchip: rk3528: add slab.h header includeHeiko Stuebner1-0/+1
2025-05-15clk: rockchip: rk3576: add missing slab.h includeHeiko Stuebner1-0/+1
2025-05-15clk: meson: Do not enable by default during compile testingKrzysztof Kozlowski1-8/+8
2025-05-15clk: meson-g12a: add missing fclk_div2 to spiccDa Xue1-0/+1
2025-05-14clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHzVincent Knecht1-2/+2
2025-05-13clk: rockchip: rename gate-grf clk fileHeiko Stuebner2-1/+1
2025-05-13clk: rockchip: rename branch_muxgrf to branch_grf_muxHeiko Stuebner2-4/+4
2025-05-13clk: sunxi-ng: d1: Add missing divider for MMC mod clocksAndre Przywara2-19/+47
2025-05-12clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) supportRyan Walklin1-0/+25
2025-05-12clk: samsung: correct clock summary for hsi1 blockPritam Manohar Sutar1-1/+1
2025-05-10clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocksYao Zi1-1/+1
2025-05-10clk: sunxi-ng: h616: Add LVDS reset for LCD TCONChris Morgan1-0/+1
2025-05-09clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in...André Draszik1-1/+2
2025-05-08clk: rockchip: rk3036: mark ddrphy as criticalHeiko Stuebner1-0/+1
2025-05-08clk: rockchip: rk3036: fix implementation of usb480m clock muxHeiko Stuebner1-6/+4
2025-05-08clk: renesas: r9a09g047: Add XSPI clock/resetBiju Das1-0/+12
2025-05-08clk: renesas: r9a09g047: Add support for xspi mux and dividerBiju Das2-1/+33
2025-05-08clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF regionYao Zi2-6/+81
2025-05-08clk: rockchip: Support MMC clocks in GRF regionYao Zi3-7/+50
2025-05-07clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoCMichal Wilczynski1-28/+168
2025-05-07clk: sophgo: Add clock controller support for SG2044 SoCInochi Amaoto3-0/+1822
2025-05-07clk: sophgo: Add PLL clock controller support for SG2044 SoCInochi Amaoto3-0/+639
2025-05-07clk: sophgo: Add support for newly added precise compatibleInochi Amaoto1-0/+2
2025-05-07clk: davinci: Use of_get_available_child_by_name()Biju Das1-12/+14
2025-05-07clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()Henry Martin1-0/+2
2025-05-07clk: bcm: rpi: Drop module aliasStefan Wahren1-1/+0
2025-05-07clk: bcm: kona: Remove unused scaled_div_buildDr. David Alan Gilbert2-20/+0
2025-05-06clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+6
2025-05-06clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+6
2025-05-06clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+3
2025-05-06clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+18
2025-05-05clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576Nicolas Frattaroli1-0/+27
2025-05-05clk: rockchip: introduce GRF gatesNicolas Frattaroli4-1/+134
2025-05-05clk: rockchip: introduce auxiliary GRFsNicolas Frattaroli7-18/+72
2025-05-05clk: renesas: Use str_on_off() helperGeert Uytterhoeven2-2/+4
2025-05-01clk: sunxi-ng: fix order of arguments in clock macroAndre Przywara1-2/+1
2025-04-30clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definitionShin Son1-1/+1
2025-04-30clk: samsung: exynosautov920: add cpucl1/2 clock supportShin Son1-0/+206
2025-04-27clk: samsung: exynosautov920: add cpucl0 clock supportShin Son1-0/+130
2025-04-27clk: sunxi: Do not enable by default during compile testingKrzysztof Kozlowski1-5/+5
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-22 00:52:47 +0300