summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas/r8a779h0-cpg-mssr.c
AgeCommit message (Collapse)AuthorFilesLines
2025-02-03clk: renesas: r8a779h0: Add VSPX clockNiklas Söderlund1-0/+1
Add the VSPX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115175927.3714357-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add FCPVX clockNiklas Söderlund1-0/+1
Add the FCPVX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115175927.3714357-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add ISP core clocksNiklas Söderlund1-0/+1
Add the ISP core module clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r8a779h0: Add display clocksTomi Valkeinen1-0/+4
Add display related clocks for DU, DSI, FCPVD, and VSPD. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-5-d74c2166fa15@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-14clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocksGeert Uytterhoeven1-6/+4
Early revisions of the R-Car V4M Series Hardware User’s Manual contained an incorrect formula for the CPU core clocks: ZCnφ = (PLL2VCO x 1/2) x mult/32 Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the parent clock. In Rev.0.70 of the documentation, the formula was corrected to: ZCnφ = (PLL2VCO x 1/4) x mult/32 As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2, the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4 (and Gen3) SoCs. Reported-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
2024-08-20clk: renesas: r8a779h0: Add CANFD clockCong Dang1-0/+1
Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be
2024-08-02clk: renesas: r8a779h0: Add PWM clockCong Dang1-0/+1
Add the module clock used by the PWM timers on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> [wsa: rebased] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240725194906.14644-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-30clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven1-5/+5
The default PLL2/3/4/6 multiplier and divider configurations are no longer used after the conversion to fixed or variable fractional PLL clock types. Note that the default configurations are still documented in the comments above the individual rcar_gen4_cpg_pll_config instances. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven1-5/+5
Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4, and PLL6 as variable fractional PLLs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/3beac7c44534ed153ce7cea5c31f4b0bb7b16ab0.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven1-6/+6
Add symbolic definitions for common CPG registers. Replace hardcoded register offsets by the new definitions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/8ae48a5dac59cb5723fbca3842b93a9e51ffe1ca.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779h0: Initial clock descriptions should be __initconstGeert Uytterhoeven1-3/+3
r8a779h0_core_clks[], r8a779h0_mod_clks[], and cpg_pll_configs[] are only used during initialization. Hence make them __initconst, so they will be freed later. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/35bbcfb914ddb377fa77e3425e4e7e232c7c2cf9.1720794214.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779h0: Add PCIe clockYoshihiro Shimoda1-0/+1
Add the PCIe module clock, which is used by the PCIe module on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240704061720.1444755-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-27clk: renesas: r8a779h0: Add Audio clocksKuninori Morimoto1-0/+2
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/87h6djkxf2.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-24clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in commentsGeert Uytterhoeven1-3/+3
The multipliers for PLL2 and PLL4 as listed in the comments for the cpg_pll_configs[] array are incorrect. Fix them. Note that the actual values in the tables were correct. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
2024-06-11clk: renesas: r8a779h0: Add VIN clocksNiklas Söderlund1-0/+16
Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240606170858.1694652-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-03clk: renesas: r8a779h0: Add CSI-2 clocksNiklas Söderlund1-0/+2
Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240527131541.1676525-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-03clk: renesas: r8a779h0: Add ISPCS clocksNiklas Söderlund1-0/+2
Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240527131541.1676525-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-04-23clk: renesas: r8a779h0: Add INTC-EX clockCong Dang1-0/+1
Add the module clock used by the Interrupt Controller for External Devices (INTC-EX) aka IRQC on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e260fd8eac0187c690ac6c62673b29f97e2ad5a4.1713279470.git.geert+renesas@glider.be
2024-04-23clk: renesas: r8a779h0: Add MSIOF clocksCong Dang1-0/+6
Add the module clocks used by the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/86ce05ae274d384c5221bd136415a7b0a1579592.1713279332.git.geert+renesas@glider.be
2024-04-08clk: renesas: r8a779h0: Add timer clocksThanh Quan1-0/+9
Add the module clocks used by Timer (CMT/TMU) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/79a66e8ff84378d7f65d5f55cfb01b9b745edd12.1712068639.git.geert+renesas@glider.be
2024-04-02clk: renesas: r8a779h0: Add SCIF clocksGeert Uytterhoeven1-0/+4
Add the module clocks used by the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/82d731edd4ae4a8cd7683368131095777f4fa172.1709741224.git.geert+renesas@glider.be
2024-03-26clk: renesas: r8a779h0: Add thermal clockGeert Uytterhoeven1-0/+1
Add the module clock used by the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) on the Renesas R-Car V4M (R8A779H0) SoC. Based on a patch in the BSP by Cong Dang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/befac3e8342cd552f580d34be863ef84403c541f.1709722056.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add RPC-IF clockCong Dang1-0/+1
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/07a72378ca64b44341af960f042a6efd41d10dc3.1708354355.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add SYS-DMAC clocksCong Dang1-0/+2
Add the module clocks used by the Direct Memory Access Controllers for System (SYS-DMAC) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/0285ef5d0c0c9d232e196559c9130ab46733d7f7.1707915706.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add SDHI clockCong Dang1-0/+1
Add the SDHI module clock, which is used by the SD Card/MMC Interface on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3a604a6924043775c2ed0630b1c5c29be2d1a5b9.1707915642.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add EtherAVB clocksCong Dang1-0/+3
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a5b4252d9822ded3fd523bc35417306cae2ec2bd.1707661303.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add I2C clocksCong Dang1-0/+4
Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/7a76dadbce24c81dd2bee68765a0b41beca2d565.1706790236.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add watchdog clockCong Dang1-0/+1
Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add PFC/GPIO clocksCong Dang1-0/+3
Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/a7d8f4111b87decb825db5ed310de8294f90b9f9.1706266196.git.geert+renesas@glider.be
2024-01-31clk: renesas: cpg-mssr: Add support for R-Car V4MCong Dang1-0/+241
Initial CPG support for the R-Car V4M (R8A779H0). Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-12 14:55:48 +0300