| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-06-10 | clocksource/drivers/timer-riscv: Use per-CPU timer interrupt | Anup Patel | 1 | -2/+0 |
| 2020-06-10 | irqchip: RISC-V per-HART local interrupt controller driver | Anup Patel | 1 | -2/+0 |
| 2020-06-10 | RISC-V: self-contained IPI handling routine | Anup Patel | 1 | -1/+0 |
| 2019-10-28 | riscv: add missing header file includes | Paul Walmsley | 1 | -0/+3 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
| 2018-08-13 | RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h | Christoph Hellwig | 1 | -4/+0 |
| 2018-08-13 | RISC-V: simplify software interrupt / IPI code | Christoph Hellwig | 1 | -0/+1 |
| 2017-09-27 | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 1 | -0/+28 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |