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path: root/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
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Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h')
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h23
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 3ba169639f54..27cecf9688cc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -438,9 +438,11 @@ struct mclock_latency_table {
};
enum smu_reset_mode {
- SMU_RESET_MODE_0,
- SMU_RESET_MODE_1,
- SMU_RESET_MODE_2,
+ SMU_RESET_MODE_0,
+ SMU_RESET_MODE_1,
+ SMU_RESET_MODE_2,
+ SMU_RESET_MODE_3,
+ SMU_RESET_MODE_4,
};
enum smu_baco_state {
@@ -1228,12 +1230,18 @@ struct pptable_funcs {
* @mode1_reset_is_support: Check if GPU supports mode1 reset.
*/
bool (*mode1_reset_is_support)(struct smu_context *smu);
+
/**
* @mode2_reset_is_support: Check if GPU supports mode2 reset.
*/
bool (*mode2_reset_is_support)(struct smu_context *smu);
/**
+ * @link_reset_is_support: Check if GPU supports link reset.
+ */
+ bool (*link_reset_is_support)(struct smu_context *smu);
+
+ /**
* @mode1_reset: Perform mode1 reset.
*
* Complete GPU reset.
@@ -1251,6 +1259,13 @@ struct pptable_funcs {
int (*enable_gfx_features)(struct smu_context *smu);
/**
+ * @link_reset: Perform link reset.
+ *
+ * The gfx device driver reset
+ */
+ int (*link_reset)(struct smu_context *smu);
+
+ /**
* @get_dpm_ultimate_freq: Get the hard frequency range of a clock
* domain in MHz.
*/
@@ -1601,7 +1616,9 @@ int smu_get_power_limit(void *handle,
bool smu_mode1_reset_is_support(struct smu_context *smu);
bool smu_mode2_reset_is_support(struct smu_context *smu);
+bool smu_link_reset_is_support(struct smu_context *smu);
int smu_mode1_reset(struct smu_context *smu);
+int smu_link_reset(struct smu_context *smu);
extern const struct amd_ip_funcs smu_ip_funcs;