diff options
| author | Ce Sun <cesun102@amd.com> | 2024-11-22 10:19:16 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-04-07 22:18:31 +0300 |
| commit | 921c040efeca35e21a836aa80fb2e3a1b8f64c97 (patch) | |
| tree | bda283b8c622e822796d1afa656810f04a54d591 /drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | |
| parent | 8e0793b6c58b7a67df21e092d90d9f93f6d35404 (diff) | |
| download | linux-921c040efeca35e21a836aa80fb2e3a1b8f64c97.tar.xz | |
drm/amd/pm: Add link reset for SMU 13.0.6
Add link reset implementation
Signed-off-by: Ce Sun <cesun102@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 3ba169639f54..27cecf9688cc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -438,9 +438,11 @@ struct mclock_latency_table { }; enum smu_reset_mode { - SMU_RESET_MODE_0, - SMU_RESET_MODE_1, - SMU_RESET_MODE_2, + SMU_RESET_MODE_0, + SMU_RESET_MODE_1, + SMU_RESET_MODE_2, + SMU_RESET_MODE_3, + SMU_RESET_MODE_4, }; enum smu_baco_state { @@ -1228,12 +1230,18 @@ struct pptable_funcs { * @mode1_reset_is_support: Check if GPU supports mode1 reset. */ bool (*mode1_reset_is_support)(struct smu_context *smu); + /** * @mode2_reset_is_support: Check if GPU supports mode2 reset. */ bool (*mode2_reset_is_support)(struct smu_context *smu); /** + * @link_reset_is_support: Check if GPU supports link reset. + */ + bool (*link_reset_is_support)(struct smu_context *smu); + + /** * @mode1_reset: Perform mode1 reset. * * Complete GPU reset. @@ -1251,6 +1259,13 @@ struct pptable_funcs { int (*enable_gfx_features)(struct smu_context *smu); /** + * @link_reset: Perform link reset. + * + * The gfx device driver reset + */ + int (*link_reset)(struct smu_context *smu); + + /** * @get_dpm_ultimate_freq: Get the hard frequency range of a clock * domain in MHz. */ @@ -1601,7 +1616,9 @@ int smu_get_power_limit(void *handle, bool smu_mode1_reset_is_support(struct smu_context *smu); bool smu_mode2_reset_is_support(struct smu_context *smu); +bool smu_link_reset_is_support(struct smu_context *smu); int smu_mode1_reset(struct smu_context *smu); +int smu_link_reset(struct smu_context *smu); extern const struct amd_ip_funcs smu_ip_funcs; |