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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-05-01 11:34:49 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 13:10:21 +0300 |
| commit | b67685300478ff768bde0d06a2a664a66223945f (patch) | |
| tree | b28f9c7aca4533cde60364e45263a5d848451352 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 14d8857d8266bce49dc4ee0d71e6cd79335d7c8c (diff) | |
| download | linux-b67685300478ff768bde0d06a2a664a66223945f.tar.xz | |
clk: renesas: r9a07g043: Add TSU clock and reset entry
Add TSU clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions