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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-05-01 11:34:48 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 13:10:21 +0300 |
| commit | 14d8857d8266bce49dc4ee0d71e6cd79335d7c8c (patch) | |
| tree | 273ac1de876b92a54caf39cd8fe5327e13d7787f /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 4e683604cfc1322f609afcbe053e6821832d5f19 (diff) | |
| download | linux-14d8857d8266bce49dc4ee0d71e6cd79335d7c8c.tar.xz | |
clk: renesas: r9a07g043: Add RSPI clock and reset entries
Add RSPI{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions