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| author | Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2022-11-11 08:37:09 +0300 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2022-11-11 21:34:02 +0300 |
| commit | 7c7c3a79213e6737b9dda4ec144555d4b446dd22 (patch) | |
| tree | f4c51734ad99f3680a48e9942377db58425c5408 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 560e9ce100c4bcbab0d5f9f18f01006f2abffef8 (diff) | |
| download | linux-7c7c3a79213e6737b9dda4ec144555d4b446dd22.tar.xz | |
dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge
Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
dt binding.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221111053709.1474323-2-thippeswamy.havalige@amd.com
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions