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| author | Frank Li <Frank.Li@nxp.com> | 2024-10-16 23:31:12 +0300 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2024-10-23 17:53:39 +0300 |
| commit | b01a731a4a5e3e8b6bc53ed80dbc6f69c42cb6d2 (patch) | |
| tree | 8a99f08acab51b18cf534c98ddcfa18f360c90e5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 9ec22ac4fe766c6abba845290d5139a3fbe0153b (diff) | |
| download | linux-b01a731a4a5e3e8b6bc53ed80dbc6f69c42cb6d2.tar.xz | |
dt-bindings: memory: fsl: Add compatible string nxp,imx9-memory-controller
iMX9 memory controller is similar with other layerscape chips. But some
register layout has a little bit difference, so add new compatible string
'nxp,imx9-memory-controller' for it.
imx9 need two 'reg', one for DDR controller and the other is ECC inject
engine register space. Keep the same restriction for other compatible
string.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241016-imx95_edac-v3-4-86ae6fc2756a@nxp.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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