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author | Priyanka Singh <priyanka.singh@nxp.com> | 2024-10-16 23:31:11 +0300 |
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committer | Borislav Petkov (AMD) <bp@alien8.de> | 2024-10-23 17:52:58 +0300 |
commit | 9ec22ac4fe766c6abba845290d5139a3fbe0153b (patch) | |
tree | ab7fdfc52d257ed815870f760ec09367bc9cc636 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 5d9aeaa607cbe77456ea6c44dfb725f86ea064ea (diff) | |
download | linux-9ec22ac4fe766c6abba845290d5139a3fbe0153b.tar.xz |
EDAC/fsl_ddr: Fix bad bit shift operations
Fix undefined behavior caused by left-shifting a negative value in the
expression:
cap_high ^ (1 << (bad_data_bit - 32))
The variable bad_data_bit ranges from 0 to 63. When it is less than 32,
bad_data_bit - 32 becomes negative, and left-shifting by a negative
value in C is undefined behavior.
Fix this by combining cap_high and cap_low into a 64-bit variable.
[ bp: Massage commit message, simplify error bits handling. ]
Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx")
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20241016-imx95_edac-v3-3-86ae6fc2756a@nxp.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions