i2c: cadence: Allow to specify the FIFO depth

The FIFO depth is a synthesis configuration parameters of the Cadence I2C
IP. Different SoCs might use different values for these parameters.

Currently the driver has the FIFO depth hardcoded to 16. Trying to use the
driver with an IP instance that uses smaller values for these will work for
short transfers. But longer transfers will fail.

Introduce a new devicetree property that allows to describe the FIFO depth
of the I2C controller.

These changes have been tested with
1) The Xilinx MPSoC for which this driver was originally written which has
   the previous hardcoded settings of 16 and 255.
2) Another instance of the Cadence I2C IP with FIFO depth of 8 and maximum
   transfer length of 16.

Without these changes the latter would fail for I2C transfers longer than
8. With the updated driver both work fine even for longer transfers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>

0 files changed, 0 insertions, 0 deletions