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authorLars-Peter Clausen <lars@metafoo.de>2023-03-17 17:54:39 +0300
committerWolfram Sang <wsa@kernel.org>2023-03-29 22:16:50 +0300
commit6ff0ddb3051e33372a22b1fac11ee74315f9d12e (patch)
treec7cc2f8d330df359decdc89b6cc531d44056df63 /tools/perf/scripts/python/export-to-sqlite.py
parent0cc98416709210e93e0ae154b336f954df298b6c (diff)
downloadlinux-6ff0ddb3051e33372a22b1fac11ee74315f9d12e.tar.xz
dt-bindings: i2c: cadence: Document `fifo-depth` property
The depth of the FIFO of the Cadence I2C controller IP is a synthesis configuration parameter. Different instances of the IP can have different values. For correct operation software needs to be aware of the size of the FIFO. Add the documentation for the devicetree property that describes the FIFO depth of the IP core. The default value of 16 is for backwards compatibility reasons with existing hardware descriptions where this property is not specified and software has assumed that the FIFO depth is 16. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Wolfram Sang <wsa@kernel.org>
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