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| author | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-07-15 06:53:25 +0300 |
|---|---|---|
| committer | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-07-20 11:48:00 +0300 |
| commit | 7ab7898ae6ccd44551acd1cde1cc7a6b5039f6b4 (patch) | |
| tree | 9d38e225ba085ca430389b9a9aeba1b10f064f24 /drivers/usb/cdns3/cdns3-debug.h | |
| parent | 30eb809e182f1fcfa797f60f9e622ac037486b19 (diff) | |
| download | linux-7ab7898ae6ccd44551acd1cde1cc7a6b5039f6b4.tar.xz | |
clk:starfive:Add PLL2 frequency controller
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, also could read or set PLL1 clock's
rate by reading or setting syscon registers.
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions