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| author | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-07-11 11:46:18 +0300 |
|---|---|---|
| committer | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-07-20 11:47:43 +0300 |
| commit | 30eb809e182f1fcfa797f60f9e622ac037486b19 (patch) | |
| tree | 77c224f69ffeb96f2a47f19db999e9c20f2f370d /drivers/usb/cdns3/cdns3-debug.h | |
| parent | c0bb15fdbe1f0853a202d083c1cc399f8330b97d (diff) | |
| download | linux-30eb809e182f1fcfa797f60f9e622ac037486b19.tar.xz | |
clk:starfive:Add PLL0 frequency controller
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, could read or set PLL0 clock's
rate by reading or setting syscon registers.
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions