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| author | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-07-15 11:51:21 +0300 |
|---|---|---|
| committer | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-07-20 11:48:13 +0300 |
| commit | 749c585f1c93bdb9cd03d9872e14e9110f31fb70 (patch) | |
| tree | 6eab4fbd1cfa9b47ce04e439dfcd021455986489 /drivers/usb/cdns3/cdns3-debug.h | |
| parent | 7ab7898ae6ccd44551acd1cde1cc7a6b5039f6b4 (diff) | |
| download | linux-749c585f1c93bdb9cd03d9872e14e9110f31fb70.tar.xz | |
clk:starfive:Set PLL2 frequency when clock tree registering
In the file drivers/clk/starfive/clk-starfive-jh7110-pll.h,
If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original.
If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2
frequency will be set the new rate during clock tree registering.
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions