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authorHarigovindan P <harigovi@codeaurora.org>2020-02-06 12:12:01 +0300
committerRob Clark <robdclark@chromium.org>2020-02-14 00:49:52 +0300
commitc6659785dfb3f8d75f1fe637e4222ff8178f5280 (patch)
tree72c89f97d95c47587fad7e817a21d1631a9d1d71 /drivers/gpu/drm/msm
parenta1028dcfd0dd97884072288d0c8ed7f30399b528 (diff)
downloadlinux-c6659785dfb3f8d75f1fe637e4222ff8178f5280.tar.xz
drm/msm/dsi/pll: call vco set rate explicitly
For a given byte clock, if VCO recalc value is exactly same as vco set rate value, vco_set_rate does not get called assuming VCO is already set to required value. But Due to GDSC toggle, VCO values are erased in the HW. To make sure VCO is programmed correctly, we forcefully call set_rate from vco_prepare. Signed-off-by: Harigovindan P <harigovi@codeaurora.org> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm')
-rw-r--r--drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 1c894548dd72..6ac04fc303f5 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -411,6 +411,12 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
if (pll_10nm->slave)
dsi_pll_enable_pll_bias(pll_10nm->slave);
+ rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
+ if (rc) {
+ pr_err("vco_set_rate failed, rc=%d\n", rc);
+ return rc;
+ }
+
/* Start PLL */
pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
0x01);