diff options
| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2024-03-20 20:56:16 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-27 00:23:34 +0300 |
| commit | 00c391102abc13763e2bfc90e05503109b19f074 (patch) | |
| tree | 105c9c3403e562878cb5c3ea7f2fbc587e7ce48d /drivers/gpu/drm/amd/display/dc/optc | |
| parent | da87132f641ed33fb65e2638d0545f55c863c5b3 (diff) | |
| download | linux-00c391102abc13763e2bfc90e05503109b19f074.tar.xz | |
drm/amd/display: Add misc DC changes for DCN401
Add miscellaneous changes to enable DCN401 init
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/optc/Makefile | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h | 3 |
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile index bb213335fb9f..29fb610c8660 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/optc/Makefile @@ -105,4 +105,10 @@ AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35) ############################################################################### ############################################################################### +OPTC_DCN401 = dcn401_optc.o + +AMD_DAL_OPTC_DCN401 = $(addprefix $(AMDDALPATH)/dc/optc/dcn401/,$(OPTC_DCN401)) + +AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN401) endif + diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 874cf5d241ad..e3e70c1db040 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -330,8 +330,6 @@ struct dcn_optc_registers { SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) - - #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ @@ -569,7 +567,6 @@ struct dcn_optc_registers { #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; - #define TG_REG_FIELD_LIST_DCN3_5(type) \ type OTG_CRC0_WINDOWA_X_START_READBACK;\ type OTG_CRC0_WINDOWA_X_END_READBACK;\ |