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| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2024-03-20 20:47:50 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-27 00:23:31 +0300 |
| commit | da87132f641ed33fb65e2638d0545f55c863c5b3 (patch) | |
| tree | c7c58262e6d554993cd40cfcda74d088c91a760d /drivers/gpu/drm/amd/display/dc/optc | |
| parent | 08502cebee7c54d58fee0a54a98064dade4cc4de (diff) | |
| download | linux-da87132f641ed33fb65e2638d0545f55c863c5b3.tar.xz | |
drm/amd/display: Add some DCN401 reg name to macro definitions
Update macros to cover DCN 4.0.1.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 2f3bd7648ba7..874cf5d241ad 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -200,6 +200,7 @@ struct dcn_optc_registers { uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; uint32_t OPTC_CLOCK_CONTROL; + uint32_t OPTC_WIDTH_CONTROL2; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -590,16 +591,22 @@ struct dcn_optc_registers { type OTG_V_COUNT_STOP;\ type OTG_V_COUNT_STOP_TIMER; +#define TG_REG_FIELD_LIST_DCN401(type) \ + type OPTC_SEGMENT_WIDTH_LAST; + + struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) + TG_REG_FIELD_LIST_DCN401(uint8_t) }; struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) + TG_REG_FIELD_LIST_DCN401(uint32_t) }; void dcn10_timing_generator_init(struct optc *optc); |