diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-04-22 13:28:43 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-04-25 11:21:35 +0300 |
| commit | b251e4c88fb443b3a44c3d04268f70e2260f1f8a (patch) | |
| tree | 256fe7a3d2ced8efff718eb5e740ce31923793d2 /drivers/clk | |
| parent | 197143feede3038350056cd1d6e7c0524fc532dd (diff) | |
| download | linux-b251e4c88fb443b3a44c3d04268f70e2260f1f8a.tar.xz | |
clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
The names of all fclk divider gate clocks follow the naming schema
"fclk_divN" and the name of all fclk fixed dividers follow the naming
schema "fclk_divN_div".
There's one exception to this rule: meson8b_fclk_div3_div's name is
"fclk_div_div3". It's child clock meson8b_fclk_div3 however references
it as "fclk_div3_div" (following the naming schema explained above).
Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
schema. This also fixes serial console on my Meson8m2 board because
"clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
and all of it's children (UART clock, SDIO MMC controller clock, ...)
are all 0.
Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index cc2992493e0b..2c4ff6192852 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -253,7 +253,7 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "fclk_div_div3", + .name = "fclk_div3_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, |