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authorBjorn Andersson <bjorn.andersson@linaro.org>2019-02-26 10:02:21 +0300
committerStephen Boyd <sboyd@kernel.org>2019-02-26 20:41:52 +0300
commit4b5a59a265f05a41df6bb3449d8c6db50577dca5 (patch)
treefe2dac41a99163bae641833cbf2304af207a2253 /drivers/clk
parentbfeffd155283772bbe78c6a05dec7c0128ee500c (diff)
downloadlinux-4b5a59a265f05a41df6bb3449d8c6db50577dca5.tar.xz
clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the PHY, describe this relationship. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index c782e62dd98b..83843896177d 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -1697,6 +1697,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
+ .parent_names = (const char *[]){ "pcie_0_pipe_clk" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1796,6 +1799,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
+ .parent_names = (const char *[]){ "pcie_1_pipe_clk" },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},