diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-05-22 19:34:53 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-07-09 14:47:22 +0300 |
| commit | 47f21315a6e4454ed9d8a450288a0989113e1e44 (patch) | |
| tree | b775418d62d71c4e8db42c6c1b2f82f32d611d8a /drivers/clk/meson/clkc.h | |
| parent | a9387f70cd27a8ca82c2141ef33787868d5c8de9 (diff) | |
| download | linux-47f21315a6e4454ed9d8a450288a0989113e1e44.tar.xz | |
clk: meson: add clk-phase clock driver
Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 2fb084330ee9..fd520ccdd1be 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -96,6 +96,13 @@ struct meson_clk_audio_div_data { u8 flags; }; +struct meson_clk_phase_data { + struct parm ph; +}; + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width); +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -119,5 +126,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_audio_divider_ro_ops; extern const struct clk_ops meson_clk_audio_divider_ops; +extern const struct clk_ops meson_clk_phase_ops; #endif /* __CLKC_H */ |