From 47f21315a6e4454ed9d8a450288a0989113e1e44 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 22 May 2018 18:34:53 +0200 Subject: clk: meson: add clk-phase clock driver Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/clkc.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/clk/meson/clkc.h') diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 2fb084330ee9..fd520ccdd1be 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -96,6 +96,13 @@ struct meson_clk_audio_div_data { u8 flags; }; +struct meson_clk_phase_data { + struct parm ph; +}; + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width); +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -119,5 +126,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_audio_divider_ro_ops; extern const struct clk_ops meson_clk_audio_divider_ops; +extern const struct clk_ops meson_clk_phase_ops; #endif /* __CLKC_H */ -- cgit v1.2.3