starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-02-02	clk: meson: rework and clean drivers dependencies	Jerome Brunet	1	-146/+0
2019-01-07	clk: meson: add dual divider clock driver	Jerome Brunet	1	-0/+19
2018-12-05	clk: meson: add clk-input helper function	Jerome Brunet	1	-0/+5
2018-11-23	clk: meson: Add vid_pll divider driver	Neil Armstrong	1	-0/+6
2018-09-26	clk: meson: clk-pll: drop hard-coded rates from pll tables	Jerome Brunet	1	-5/+3
2018-09-26	clk: meson: clk-pll: remove od parameters	Jerome Brunet	1	-8/+1
2018-09-26	clk: meson: clk-pll: add enable bit	Jerome Brunet	1	-0/+1
2018-07-09	clk: meson: remove unused clk-audio-divider driver	Jerome Brunet	1	-7/+0
2018-07-09	clk: meson: add clk-phase clock driver	Jerome Brunet	1	-0/+8
2018-05-21	clk: meson: mpll: add round closest support	Jerome Brunet	1	-0/+3
2018-05-18	clk: meson: use SPDX license identifiers consistently	Jerome Brunet	1	-12/+1
2018-03-13	clk: meson: add ROUND_CLOSEST to the pll driver	Jerome Brunet	1	-0/+2
2018-03-13	clk: meson: improve pll driver results with frac	Jerome Brunet	1	-12/+1
2018-03-13	clk: meson: remove special gp0 lock loop	Jerome Brunet	1	-2/+0
2018-03-13	clk: meson: remove obsolete cpu_clk	Jerome Brunet	1	-11/+0
2018-03-13	clk: meson: split divider and gate part of mpll	Jerome Brunet	1	-1/+0
2018-03-13	clk: meson: migrate plls clocks to clk_regmap	Jerome Brunet	1	-28/+8
2018-03-13	clk: meson: migrate the audio divider clock to clk_regmap	Jerome Brunet	1	-4/+1
2018-03-13	clk: meson: migrate mplls clocks to clk_regmap	Jerome Brunet	1	-3/+1
2018-03-13	clk: meson: add regmap helpers for parm	Jerome Brunet	1	-0/+16
2018-03-13	clk: meson: migrate gates to clk_regmap	Jerome Brunet	1	-8/+12
2018-02-12	clk: meson: add axg misc bit to the mpll driver	Jerome Brunet	1	-0/+1
2018-02-12	clk: meson: add od3 to the pll driver	Jerome Brunet	1	-0/+2
2017-12-14	clk: meson: make the spinlock naming more specific	Yixun Lan	1	-1/+1
2017-08-01	clk: meson: mpll: fix mpll0 fractional part ignored	Jerome Brunet	1	-0/+1
2017-04-07	clk: meson: add audio clock divider support	Jerome Brunet	1	-0/+10
2017-04-04	clk: meson: Add support for parameters for specific PLLs	Neil Armstrong	1	-0/+23
2017-03-27	clk: meson: mpll: add rw operation	Jerome Brunet	1	-1/+3
2017-03-27	clk: meson: fix SET_PARM macro	Jerome Brunet	1	-1/+1
2016-09-02	gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b	Alexander Müller	1	-1/+1
2016-06-23	clk: meson: fractional pll support	Michael Turquette	1	-0/+15
2016-06-23	clk: meson: add mpll support	Michael Turquette	1	-0/+10
2016-06-23	clk: meson: add peripheral gate macro	Michael Turquette	1	-0/+14
2016-06-23	clk: meson8b: clean up composite clocks	Michael Turquette	1	-56/+0
2016-06-23	clk: meson8b: clean up cpu clocks	Michael Turquette	1	-14/+11
2016-06-23	clk: meson8b: clean up fixed factor clocks	Michael Turquette	1	-19/+0
2016-06-23	clk: meson8b: clean up pll clocks	Michael Turquette	1	-27/+25
2016-06-23	clk: meson8b: clean up fixed rate clocks	Michael Turquette	1	-26/+0
2015-06-06	clk: meson: Add support for Meson clock controller	Carlo Caione	1	-0/+187