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authorPalmer Dabbelt <palmer@sifive.com>2019-09-25 03:15:56 +0300
committerPaul Walmsley <paul.walmsley@sifive.com>2019-10-01 23:16:40 +0300
commit18856604b3e7090ce42d533995173ee70c24b1c9 (patch)
tree2d52b920be2bb0dc54bb4ad0dd88413a7be5fcee /arch/riscv/include/asm/asm.h
parent54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff)
downloadlinux-18856604b3e7090ce42d533995173ee70c24b1c9.tar.xz
RISC-V: Clear load reservations while restoring hart contexts
This is almost entirely a comment. The bug is unlikely to manifest on existing hardware because there is a timeout on load reservations, but manifests on QEMU because there is no timeout. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm/asm.h')
-rw-r--r--arch/riscv/include/asm/asm.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
index 5a02b7d50940..9c992a88d858 100644
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -22,6 +22,7 @@
#define REG_L __REG_SEL(ld, lw)
#define REG_S __REG_SEL(sd, sw)
+#define REG_SC __REG_SEL(sc.d, sc.w)
#define SZREG __REG_SEL(8, 4)
#define LGREG __REG_SEL(3, 2)