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| author | Michael Neuling <mikey@neuling.org> | 2012-06-25 17:33:10 +0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-07-10 13:17:55 +0400 |
| commit | c75df6f96c59beed8632e3aced5fb4faabaa6c5b (patch) | |
| tree | b21ce9394028ec4520a71d87391dad8ab29edd67 /arch/powerpc/mm/tlb_nohash_low.S | |
| parent | 564aa5cfd3e33ef69a5ca6c170a0fe79c6805e52 (diff) | |
| download | linux-c75df6f96c59beed8632e3aced5fb4faabaa6c5b.tar.xz | |
powerpc: Fix usage of register macros getting ready for %r0 change
Anything that uses a constructed instruction (ie. from ppc-opcode.h),
need to use the new R0 macro, as %r0 is not going to work.
Also convert usages of macros where we are just determining an offset
(usually for a load/store), like:
std r14,STK_REG(r14)(r1)
Can't use STK_REG(r14) as %r14 doesn't work in the STK_REG macro since
it's just calculating an offset.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/tlb_nohash_low.S')
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 7c63c0ed4f1b..5a1285a9109f 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -313,7 +313,7 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE - PPC_TLBILX_VA(0,r3) + PPC_TLBILX_VA(R0,R3) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -364,7 +364,7 @@ _GLOBAL(_tlbil_va) beq 1f rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ - PPC_TLBILX_VA(0,r3) + PPC_TLBILX_VA(R0,R3) msync isync wrtee r10 @@ -379,7 +379,7 @@ _GLOBAL(_tlbivax_bcast) beq 1f rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ - PPC_TLBIVAX(0,r3) + PPC_TLBIVAX(R0,R3) eieio tlbsync sync |