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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-05-07 16:24:49 +0300
committerSimon Horman <horms+renesas@verge.net.au>2018-05-14 17:40:40 +0300
commitcad8e5a7a1e27e9efe4e706ace75e0826a79707f (patch)
tree044b3185cdeb275943c84e69191b3971dd3a1623 /arch/arm
parentc02cc235a215e9c518f98da25753b9e02bb7144f (diff)
downloadlinux-cad8e5a7a1e27e9efe4e706ace75e0826a79707f.tar.xz
ARM: dts: r7s72100: Correct RTC interrupt types
According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware User's Manual rev. 3.00, the realtime clock interrupts are level not edge interrupts. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index c7b3dca6d81c..eb2e6f95a2e8 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -682,9 +682,9 @@
rtc: rtc@fcff1000 {
compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
reg = <0xfcff1000 0x2e>;
- interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
- GIC_SPI 277 IRQ_TYPE_EDGE_RISING
- GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "period", "carry";
clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
<&rtc_x3_clk>, <&extal_clk>;