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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-10-19 11:47:28 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-25 12:08:16 +0300 |
| commit | e200b06d8ecaa70798f45f815b2cac280a7c1b20 (patch) | |
| tree | 588d0c0884b82358f77e02ca114cd3a80c8c996c | |
| parent | ba73f1ead5db93abe955598f8f7dd9f14a28d8f6 (diff) | |
| download | linux-e200b06d8ecaa70798f45f815b2cac280a7c1b20.tar.xz | |
clk: renesas: r9a08g045: Add power domain for RTC
The RTC and VBATTB don't share the MSTOP control bit (but only the bus
clock and the reset signal). As the MSTOP control is modeled though power
domains add power domain support for the RTC device available on the
Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a08g045-cpg.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index f5f454832bb5..b2ae8cdc4723 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -309,6 +309,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), + DEF_PD("rtc", R9A08G045_PD_RTC, + DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0), }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { |